A 2.5 GHz All-Digital Delay-Locked Loop in 0.13 µm CMOS Technology.

Rong-Jyi Yang Shen-Iuan Liu

Published in: IEEE J. Solid State Circuits (2007)

Keyphrases

cmos technology
power dissipation
mixed signal
low power
clock frequency
power consumption
high speed
spl times
low voltage
multi channel
cmos image sensor
parallel processing
low cost
image sequences
hardware and software