Chao-Chyun Chen

Publication Activity (10 Years)

Years Active: 2007-2020
Publications (10 Years): 3

Top Topics

Temporal Continuity

Vlsi Architecture

Top Venues

J. Signal Process. Syst.

Circuits Syst. Signal Process.

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Yu-Hsuan Lee, Cheng-Hung Lin, Chao-Chyun Chen, Shu-Yen Lin, Bo-Siang Huang
Correction to: the Video Spatial Error Concealment Algorithm Using Separately-Directional Interpolation Technique. J. Signal Process. Syst. 92 (4) (2020)
Yu-Hsuan Lee, Cheng-Hung Lin, Chao-Chyun Chen, Shu-Yen Lin, Bo-Siang Huang
The Video Spatial Error Concealment Algorithm Using Separately-Directional Interpolation Technique. J. Signal Process. Syst. 88 (1) (2017)
Wei-Cheng Chen, Chao-Chyun Chen, Chia-Yu Yao, Rong-Jyi Yang
A Fast-Transient Wide-Voltage-Range Digital-Controlled Buck Converter With Cycle-Controlled DPWM. IEEE Trans. Very Large Scale Integr. Syst. 24 (1) (2016)
Yu-Hsuan Lee, Chao-Chyun Chen, Yi-Lun You
Design of VLSI Architecture of Autocorrelation-Based Lossless Recompression Engine for Memory-Efficient Video Coding Systems. Circuits Syst. Signal Process. 33 (2) (2014)
Chun-Yen Wu, Chi-Nan Chuang, Chao-Chyun Chen, I-Chyn Wey
A wide-range and fast-locking frequency synthesizer for Wimax and WLAN applications. GCCE (2014)
Chao-Chyun Chen, Jiun-Wei Yang, Nai-Shen Kuo
A modified multi-fingers stru cture for power transistor in 0.16μm CMOS process. ICCE-TW (2014)
Wei-Cheng Chen, Rong-Jyi Yang, Chia-Yu Yao, Chao-Chyun Chen
A wide-range all-digital delay-locked loop using fast-lock variable SAR algorithm. ISPACS (2012)
Chao-Chyun Chen, Shen-Iuan Liu
An Infinite Phase Shift Delay-Locked Loop With Voltage-Controlled Sawtooth Delay Line. IEEE J. Solid State Circuits 43 (11) (2008)
Chao-Chyun Chen, Jung-Yu Chang, Shen-Iuan Liu
A DLL-Based Variable-Phase Clock Buffer. IEEE Trans. Circuits Syst. II Express Briefs (12) (2007)