Ivan Siu-Chuang Lu

Publication Activity (10 Years)

Years Active: 2005-2022
Publications (10 Years): 2

Top Topics

Reference Trajectory

Linear Quadratic

Top Venues

IEEE J. Solid State Circuits

Publications

Venumadhav Bhagavatula, Fan Zhang, Che-Chun Kuo, Anirban Sarkar, Ashutosh Verma, Tienyu Chang, Xiaohua Yu, Daeyoung Yoon, Ivan Siu-Chuang Lu, Sang Won Son, Thomas Byunghak Cho
A 5G FR2 Power-Amplifier With an Integrated Power-Detector for Closed-Loop EIRP Control. IEEE J. Solid State Circuits 57 (5) (2022)
Wanghua Wu, Chih-Wei Yao, Kunal Godbole, Ronghua Ni, Pei-Yuan Chiang, Yongping Han, Yongrong Zuo, Ashutosh Verma, Ivan Siu-Chuang Lu, Sang Won Son, Thomas Byunghak Cho
Analog Fractional- $N$ Sampling PLL With a Highly Linear DTC Incorporating Background DTC Gain Calibration and Reference Clock Duty Cycle Correction. IEEE J. Solid State Circuits 54 (5) (2019)
Chi-Yao Yu, Ivan Siu-Chuang Lu, Yen-Horng Chen, Lan-chou Cho, Chih-hao Eric Sun, Chih-Chun Tang, Hsiang-Hui Chang, Wen-Chang Lee, Sheng-Jui Huang, Tzung-Han Wu, Chinq-Shiun Chiu, George Chien
A SAW-Less GSM/GPRS/EDGE Receiver Embedded in 65-nm SoC. IEEE J. Solid State Circuits 46 (12) (2011)
Ivan Siu-Chuang Lu, Chi-Yao Yu, Yen-Horng Chen, Lan-chou Cho, Chih-hao Eric Sun, Chih-Chun Tang, George Chien
A SAW-less GSM/GPRS/EDGE receiver embedded in a 65nm CMOS SoC. ISSCC (2011)
Ivan Siu-Chuang Lu, Neil Weste, Sri Parameswaran
A Power-Efficient 5.6-GHz Process-Compensated CMOS Frequency Divider. IEEE Trans. Circuits Syst. II Express Briefs (4) (2007)
Ivan Siu-Chuang Lu, Neil Weste, Sri Parameswaran
ADC Precision Requirement for Digital Ultra-Wideband Receivers with Sublinear Front-Ends: A Power and Performance Perspective. VLSI Design (2006)
Ivan Siu-Chuang Lu, Neil Weste, Sri Parameswaran
The effect of receiver front-end non-linearity on DS-UWB systems operating in the 3 to 4 GHz band. WCNC (2005)