Analog Fractional- $N$ Sampling PLL With a Highly Linear DTC Incorporating Background DTC Gain Calibration and Reference Clock Duty Cycle Correction.
Wanghua WuChih-Wei YaoKunal GodboleRonghua NiPei-Yuan ChiangYongping HanYongrong ZuoAshutosh VermaIvan Siu-Chuang LuSang Won SonThomas Byunghak ChoPublished in: IEEE J. Solid State Circuits (2019)