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A wide-range delay-locked loop with a fixed latency of one clock cycle.
Hsiang-Hui Chang
Jyh-Woei Lin
Ching-Yuan Yang
Shen-Iuan Liu
Published in:
IEEE J. Solid State Circuits (2002)
Keyphrases
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wide range
clock frequency
power consumption
high speed
prefetching
feedback loop
fixed number
low latency
response time
duty cycle
databases
real world
transmission power