Ching-Yuan Yang

Publication Activity (10 Years)

Years Active: 1998-2023
Publications (10 Years): 22

Top Topics

Fish Eye Lenses

Communication Systems

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Wan-Yu You, Ching-Yuan Yang
Behavior Simulation of SSC Generator With Adjustable Modulation Frequency and Depth. ISOCC (2023)
Shu-Chi Wang, Ching-Yuan Yang
Behavior Simulation of CDR for SSC System With a Compact Quarter-Rate Linear Phase Detector. ISOCC (2023)
Ke-Chiao Chou, Chun-Hung Lin, Ching-Yuan Yang
A 30-GHz Frequency Doubler Using a Current Folding Technique in 90-nm CMOS Technology. MOCAST (2023)
Tsung-Ying Chen, Ching-Yuan Yang, Dung-An Wang
A 80-MHz 91.2 ppm/°C Self-Biased Frequency-Locked-Loop Timer. ISOCC (2022)
Shao-Yu Shu, Chun-Hung Lin, Ching-Yuan Yang
A 5-GHz Sub-Sampling Phase-Locked Loop With Pulse-Width to Current Conversion. VLSI-DAT (2022)
Ching-Yuan Yang, Miao-Shan Li, Ai-Jia Chuang
A Wide-Range Folded-Tuned Dual-DLL-Based Clock-Deskewing Circuit for Core-to-Core Links. IEEE Trans. Very Large Scale Integr. Syst. 29 (5) (2021)
Yong-Zheng Wang, Ching-Yuan Yang
A Self Synchronized-Switch Rectifier for Piezoelectric-Vibration Energy-Harvesting Systems. ISOCC (2021)
Yen-Kuei Lu, Miao-Shan Li, Ching-Yuan Yang, Chin-Lung Lin
A 2.7-Gb/s Multiplexed-DLL-Based CDR Circuit for ±10% Clock-Embedded Spread-Spectrum Modulation Depth. A-SSCC (2021)
Hao-Hsiang Hsu, Ching-Yuan Yang, Dung-An Wang
A High-Efficiency Parallel-SSHI Rectifier for Piezoelectric Energy Harvesting. ISOCC (2020)
Wan-Ling Wu, Ching-Yuan Yang, Dung-An Wang
A Flipping Active-Diode Rectifier for Piezoelectric-Vibration Energy-Harvesting. ECCTD (2020)
Wan-Ling Wu, Yong-Zheng Wang, Ching-Yuan Yang
Flipping Rectifiers for Piezoelectric Vibration Energy Harvesting. ISOCC (2019)
Po-Yu Hsieh, Shao-Yu Shu, Ching-Yuan Yang
A Spur-Suppression Technique for Frequency Synthesizer with Pulse-Width to Current Conversion. ISPACS (2019)
Miao-Shan Li, Yen-Kuei Lu, Ching-Yuan Yang, Chin-Lung Lin
PLL-Based Clock and Data Recovery for SSC Embedded Clock Systems. ISOCC (2019)
You-Sheng Lin, Miao-Shan Li, Ching-Yuan Yang
A 2.7-Gb/s Clock and Data Recovery Circuit Based on D/PLL. SoCC (2019)
Guan-Min Luo, Ching-Yuan Yang
A 10-GHz Fast-Locked All-Digital Frequency Synthesizer with Frequency-Error Detection. SoCC (2019)
Chih-Yang Lin, Cheng-Hsun Chen, Ching-Yuan Yang, Fityanul Akhyar, Chao-Yung Hsu, Hui-Fuang Ng
Cascading Convolutional Neural Network for Steel Surface Defect Detection. AHFE (14) (2019)
Yen-Chen Lin, Ching-Yuan Yang, James Chang
A 1.5-Gb/s equalizer with adaptive swing controller for TFT-LCD driver. ISOCC (2017)
Chia-Chi Liu, Ching-Yuan Yang
A 1.5-Gb/s adaptive equalizer with periodically embedded clock encoding for intra-panel interfaces. ISOCC (2017)
Ching-Yuan Yang, Jen-Yan Huang, Jun-Hong Weng
Realization of buck converter with adaptive variable-frequency control. SoCC (2017)
Ching-Yuan Yang
W2A: Analog-to-digital converters and low-noise amplifiers. SoCC (2017)
Hsuan-Yu Chang, Ching-Yuan Yang
A Reference Voltage Interpolation-Based Calibration Method for Flash ADCs. IEEE Trans. Very Large Scale Integr. Syst. 24 (5) (2016)
Po-Tsang Chen, Ching-Yuan Yang
A 90-nm CMOS Frequency Synthesizer with a Tripler for 60-GHz Wireless Communication Systems. ISVLSI (2016)
Jung-Mao Lin, Ching-Yuan Yang, Hsin-Ming Wu
A 2.5-Gb/s DLL-Based Burst-Mode Clock and Data Recovery Circuit With 4× Oversampling. IEEE Trans. Very Large Scale Integr. Syst. 23 (4) (2015)
Jung-Mao Lin, Ching-Yuan Yang
A Fast-Locking All-Digital Phase-Locked Loop With Dynamic Loop Bandwidth Adjustment. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2015)
Hsuan-Yu Chang, Ching-Yuan Yang
A high-speed low-power calibrated flash ADC. ISCAS (2014)
Chih-Hsiang Chang, Ching-Yuan Yang, Yu Lee, Jun-Hong Weng, Nai-Chen Cheng
A 3.4mW 2.3-to-2.7GHz frequency synthesizer in 0.18-µm CMOS. ESSCIRC (2013)
Ai-Jia Chuang, Yu Lee, Ching-Yuan Yang
A chip-to-chip clock-deskewing circuit for 3-D ICs. ISCAS (2012)
Ching-Yuan Yang, Jia-Jiun Lin, Chih-Hsiang Chang
A 22-GHz low-power frequency synthesizer in 0.18-um CMOS. ISCIT (2012)
Jun-Hong Weng, Ching-Yuan Yang, Yi-Lin Jhu
A low-power direct digital frequency synthesizer using an analogue-sine-conversion technique. ISLPED (2011)
Ching-Yuan Yang, Jun-Hong Weng, Hsuan-Yu Chang
A 5-GHz Direct Digital Frequency Synthesizer Using an Analog-Sine-Mapping Technique in 0.35- μ m SiGe BiCMOS. IEEE J. Solid State Circuits 46 (9) (2011)
Ching-Yuan Yang, Chih-Hsiang Chang, Jun-Hong Weng, Hsin-Ming Wu
A 0.5/0.8-V 9-GHz Frequency Synthesizer With Doubling Generation in 0.13-μm CMOS. IEEE Trans. Circuits Syst. II Express Briefs (2) (2011)
Yu Lee, Ching-Yuan Yang, Nai-Chen Daniel Cheng, Ji-Jan Chen
An embedded wide-range and high-resolution CLOCK jitter measurement circuit. DATE (2010)
Ching-Yuan Yang, Chih-Hsiang Chang, Wen-Ger Wong
A Delta-Sigma PLL-Based Spread-Spectrum Clock Generator With a Ditherless Fractional Topology. IEEE Trans. Circuits Syst. I Regul. Pap. (1) (2009)
Gung-Yu Lin, Ching-Yuan Yang, Yu Lee, Jun-Hong Weng
A programmable duty cycle corrector based on delta-sigma modulated PWM mechanism. APCCAS (2008)
Chin-Sien Moo, Chun-Kai Huang, Ching-Yuan Yang
Acoustic-Resonance-Free High-Frequency Electronic Ballast for Metal Halide Lamps. IEEE Trans. Ind. Electron. 55 (10) (2008)
Ching-Yuan Yang, Chih-Hsiang Chang, Wen-Ger Wong
A 3.2-GHz Down-Spread Spectrum Clock Generator Using a Nested Fractional Topology. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2008)
Ching-Yuan Yang, Yu Lee
A PWM and PAM Signaling Hybrid Technology for Serial-Link Transceivers. IEEE Trans. Instrum. Meas. 57 (5) (2008)
Kai Pong Wu, Ching-Yuan Yang, Jung-Mao Lin
A 2.5Gb/s oversampling clock and data recovery circuit with frequency calibration technique. APCCAS (2008)
Ching-Yuan Yang, Ken-Hao Chang
Injection-Locked Clock Recovery Using a Multiplexed Oscillator for Half-Rate Data-Recovered Applications. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (1) (2008)
Meng-Ting Tsai, Ching-Yuan Yang
A Fast-Locking Agile Frequency Synthesizer for MIMO Dual-mode WiFi / WiMAX Applications. ICECS (2007)
Ching-Yuan Yang, Jung-Mao Lin
A 1.25-Gb/s Burst-Mode Half-Rate Clock and Data Recovery Circuit Using Realigned Oscillation. IEICE Trans. Electron. (1) (2007)
Jun-Hong Weng, Meng-Ting Tsai, Jung-Mao Lin, Ching-Yuan Yang
A 1.8-Gb/s burst-mode clock and data recovery circuit with a 1/4-rate clock technique. ISCAS (2006)
Meng-Ting Tsai, Ching-Yuan Yang
A frequency synthesizer realized by a transformer-based voltage-controlled oscillator for IEEE 802.11a/b/g channels. ISCAS (2006)
Chia-Chieh Tu, Ching-Yuan Yang
A 6.5-GHz LC VCO with Integrated-Transformer Tuning. APCCAS (2006)
Ching-Yuan Yang, Meng-Ting Tsai
-Tank Oscillators Using a Tunable Inductor Technique. IEICE Trans. Electron. (11) (2006)
Hsin-Ming Wu, Ching-Yuan Yang
A 3.125-GHz Limiting Amplifier for Optical Receiver System. APCCAS (2006)
Ching-Yuan Yang, Yu Lee, Cheng-Hsing Lee
A CMOS Clock and Data Recovery Circuit with a Half-Rate Three-State Phase Detector. IEICE Trans. Electron. (6) (2006)
Jun-Hong Weng, Chong-Jng Yu, Ching-Yuan Yang, Peng-Chang Yang
A low-noise microsensor amplifier with automatic gain control system. ISCAS (2006)
Ching-Yuan Yang, Yu Lee
A 0.18-µm CMOS 1-Gb/s serial link transceiver by using PWM and PAM techniques. ISCAS (2) (2005)
Ching-Yuan Yang, Jen-Wen Chen, Meng-Ting Tsai
A high-frequency phase-compensation fractional-N frequency synthesizer. ISCAS (5) (2005)
Hsiang-Hui Chang, Jyh-Woei Lin, Ching-Yuan Yang, Shen-Iuan Liu
A wide-range delay-locked loop with a fixed latency of one clock cycle. IEEE J. Solid State Circuits 37 (8) (2002)
Ching-Yuan Yang, Shen-Iuan Liu
A one-wire approach for skew-compensating clock distribution based on bidirectional techniques. IEEE J. Solid State Circuits 36 (2) (2001)
Guang-Kaai Dehng, June-Ming Hsu, Ching-Yuan Yang, Shen-Iuan Liu
Clock-deskew buffer using a SAR-controlled delay-locked loop. IEEE J. Solid State Circuits 35 (8) (2000)
Guang-Kaai Dehng, Ching-Yuan Yang, June-Ming Hsu, Shen-Iuan Liu
A 900-MHz 1-V CMOS frequency synthesizer. IEEE J. Solid State Circuits 35 (8) (2000)
Ching-Yuan Yang, Shen-Iuan Liu
Fast-switching frequency synthesizer with a discriminator-aided phase detector. IEEE J. Solid State Circuits 35 (10) (2000)
Ching-Yuan Yang, Guang-Kaai Dehng, June-Ming Hsu, Shen-Iuan Liu
New dynamic flip-flops for high-speed dual-modulus prescaler. IEEE J. Solid State Circuits 33 (10) (1998)