Clock-deskew buffer using a SAR-controlled delay-locked loop.

Guang-Kaai Dehng June-Ming Hsu Ching-Yuan Yang Shen-Iuan Liu

Published in: IEEE J. Solid State Circuits (2000)

Keyphrases

buffer size
loss probability
synthetic aperture radar
clock frequency
sar images
high speed
power consumption
parameter estimation
image reconstruction
finite buffer
sea ice
neural network
duty cycle
waiting times
buffer overflow
sar imagery
synthetic aperture radar images
feedback loop
least squares