Jung-Mao Lin

Publication Activity (10 Years)

Years Active: 2006-2015
Publications (10 Years): 0

Top Topics

Database Systems

Dynamic Environments

Phase Locked Loop

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Jung-Mao Lin, Ching-Yuan Yang, Hsin-Ming Wu
A 2.5-Gb/s DLL-Based Burst-Mode Clock and Data Recovery Circuit With 4× Oversampling. IEEE Trans. Very Large Scale Integr. Syst. 23 (4) (2015)
Jung-Mao Lin, Ching-Yuan Yang
A Fast-Locking All-Digital Phase-Locked Loop With Dynamic Loop Bandwidth Adjustment. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2015)
Jung-Mao Lin, Hsin-Yi Yu, Yu-Jen Wu, Hsi-Pin Ma
A Power Efficient Baseband Engine for Multiuser Mobile MIMO-OFDMA Communications. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2010)
Jung-Mao Lin, Hsi-Pin Ma, Danijela Cabric
A Reliable Adaptive Multitaper Spectral Detector in Wideband Strong Interference Environments. GLOBECOM (2010)
Jung-Mao Lin, Hsi-Pin Ma
A high performance baseband transceiver for SISO-/MIMO-OFDA uplink communications. IEEE Trans. Wirel. Commun. 8 (7) (2009)
Tsung-Wei Chiang, Jung-Mao Lin, Hsi-Pin Ma
Optimal Detector for Multitaper Spectrum Estimator in Cognitive Radios. GLOBECOM (2009)
Yu-Jen Wu, Jung-Mao Lin, Hsin-Yi Yu, Hsi-Pin Ma
A baseband Testbed for Uplink Mobile MIMO WiMAX Communications. ISCAS (2009)
Yu-Jen Wu, Jung-Mao Lin, Hsin-Yi Yu, Hsi-Pin Ma
Live Demonstration: A Baseband Testbed for Uplink Mobile MIMO WiMAX Communications. ISCAS (2009)
Kai Pong Wu, Ching-Yuan Yang, Jung-Mao Lin
A 2.5Gb/s oversampling clock and data recovery circuit with frequency calibration technique. APCCAS (2008)
Jung-Mao Lin, Hsi-Pin Ma, Pangan Ting
A Baseband Transceiver for IEEE 802.16e-2005 MIMO-OFDMA Uplink Communications. GLOBECOM (2007)
Ching-Yuan Yang, Jung-Mao Lin
A 1.25-Gb/s Burst-Mode Half-Rate Clock and Data Recovery Circuit Using Realigned Oscillation. IEICE Trans. Electron. (1) (2007)
Jun-Hong Weng, Meng-Ting Tsai, Jung-Mao Lin, Ching-Yuan Yang
A 1.8-Gb/s burst-mode clock and data recovery circuit with a 1/4-rate clock technique. ISCAS (2006)