A 1.5-Gb/s adaptive equalizer with periodically embedded clock encoding for intra-panel interfaces.

Chia-Chi Liu Ching-Yuan Yang

Published in: ISOCC (2017)

Keyphrases

high speed
computer simulation
digital images
neural network
variable length
network size
duty cycle
databases
information retrieval
information systems
power consumption
embedded systems
encoding scheme
intra coding