A 6 MHz-130 MHz DLL with a fixed latency of one clock cycle delay.

Hsiang-Hui Chang Jyh-Woei Lin Shen-Iuan Liu

Published in: CICC (2002)

Keyphrases

clock frequency
high speed
power consumption
high end
low power
high frequency
parallel computing
low latency
parallel architecture
cmos technology
fpga device
field programmable gate array
real time
fixed number
massively parallel