Yung-Yu Lin

Publication Activity (10 Years)

Years Active: 2005-2017
Publications (10 Years): 1

Top Topics

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

IEEE Trans. Circuits Syst. II Express Briefs

Publications

Chan-Hsiang Weng, Yung-Yu Lin, Tsung-Hsien Lin
A 1-V 5-MHz Bandwidth 68.3-dB SNDR Continuous-Time Delta-Sigma Modulator With a Feedback-Assisted Quantizer. IEEE Trans. Circuits Syst. I Regul. Pap. (5) (2017)
Ching-Te Wang, Yung-Yu Lin
The prediction system for data analysis of stock market by using Genetic Algorithm. FSKD (2015)
Fu-Chien Huang, Shou-Chen Hsu, Yi-Lin Tsai, Yung-Yu Lin, Tsung-Hsien Lin
LMS-based digital background linearization technique for VCO-based delta-sigma ADC. MWSCAS (2014)
Chen-Chien Lin, Chan-Hsiang Weng, Tzu-An Wei, Yung-Yu Lin, Tsung-Hsien Lin
A TDC-Based Two-Step Quantizer With Swapper Technique for a Multibit Continuous-Time Delta-Sigma Modulator. IEEE Trans. Circuits Syst. II Express Briefs (2) (2014)
Chen-Yen Ho, Wei-Shan Chan, Yung-Yu Lin, Tsung-Hsien Lin
A Quadrature Bandpass Continuous-Time Delta-Sigma Modulator for a Tri-Mode GSM-EDGE/UMTS/DVB-T Receiver. IEEE J. Solid State Circuits 46 (11) (2011)
Chen-Yen Ho, Yung-Yu Lin, Tsung-Hsien Lin
Dual-mode Continuous-Time Quadrature Bandpass ΔΣ modulator with Pseudo-random Quadrature mismatch shaping algorithm for Low-IF receiver application. ISCAS (2010)
Sheng-Jui Huang, Yung-Yu Lin
CT ΔΣ ADC with -97.7dBc THD and 80dB DR using low-latency DEM. ISSCC (2009)
Ping-Ying Wang, Hsiang Ji Hsieh, Yung-Yu Lin, Meng-Ta Yang, Hsueh-Wu Kao
A phase locked loop with a mixed mode loop filter for clock/data recovery in optical disc drives. ISCAS (5) (2005)