A Leakage-Current-Recycling Phase-Locked Loop in 65 nm CMOS Technology.

I-Ting Lee Yun-Ta Tsai Shen-Iuan Liu

Published in: IEEE J. Solid State Circuits (2012)

Keyphrases

leakage current
low voltage
cmos technology
phase locked loop
low power
power line
parallel processing
multipath
power consumption
high voltage
low cost
design considerations
power management
random access memory
silicon on insulator
image sensor
real time
wireless sensor networks
control system
image sequences