False Path and Clock Scheduling Based Yield-Aware Gate Sizing.

Jeng-Liang Tsai Dong Hyun Baik Charlie Chung-Ping Chen Kewal K. Saluja

Published in: VLSI Design (2005)

Keyphrases

scheduling problem
scheduling algorithm
shortest path
dynamic scheduling
resource allocation
high speed
power consumption
round robin
real time database systems
information systems
endpoints
parallel machines
flexible manufacturing systems
manufacturing cell
precedence constraints
response time
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