Jeng-Liang Tsai

Publication Activity (10 Years)

Years Active: 2003-2006
Publications (10 Years): 0

Publications

Lizheng Zhang, Jeng-Liang Tsai, Weijen Chen, Yuhen Hu, Charlie Chung-Ping Chen
Convergence-provable statistical timing analysis with level-sensitive latches and feedback loops. ASP-DAC (2006)
Pei-Yu Huang, Yu-Min Lee, Jeng-Liang Tsai, Charlie Chung-Ping Chen
Simultaneous area minimization and decaps insertion for power delivery network using adjoint sensitivity analysis with IEKS method. ISCAS (2006)
Jeng-Liang Tsai, Charlie Chung-Ping Chen, Guoqiang Chen, Brent Goplen, Haifeng Qian, Yong Zhan, Sung-Mo Kang, Martin D. F. Wong, Sachin S. Sapatnekar
Temperature-Aware Placement for SOCs. Proc. IEEE 94 (8) (2006)
Jeng-Liang Tsai, Charlie Chung-Ping Chen
Process-variation robust and low-power zero-skew buffered clock-tree synthesis using projected scan-line sampling. ASP-DAC (2005)
Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja
Yield-Driven, False-Path-Aware Clock Skew Scheduling. IEEE Des. Test Comput. 22 (3) (2005)
Jeng-Liang Tsai, Lizheng Zhang
Statistical timing analysis driven post-silicon-tunable clock-tree synthesis. ICCAD (2005)
Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja
False Path and Clock Scheduling Based Yield-Aware Gate Sizing. VLSI Design (2005)
Ting-Yuan Wang, Jeng-Liang Tsai, Charlie Chung-Ping Chen
Thermal and Power Integrity Based Power/Ground Networks Optimization. DATE (2004)
Ting-Yuan Wang, Jeng-Liang Tsai, Charlie Chung-Ping Chen
Sensitivity guided net weighting for placement driven synthesis. ISPD (2004)
Jeng-Liang Tsai, Tsung-Hao Chen, Charlie Chung-Ping Chen
Zero skew clock-tree optimization with buffer insertion/sizing and wire sizing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23 (4) (2004)
Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja
A yield improvement methodology using pre- and post-silicon statistical clock scheduling. ICCAD (2004)
Tsung-Hao Chen, Jeng-Liang Tsai, Tanay Karnik
HiSIM: hierarchical interconnect-centric circuit simulator. ICCAD (2004)
Jeng-Liang Tsai, Tsung-Hao Chen, Charlie Chung-Ping Chen
Optimal minimum-delay/area zero-skew clock tree wire-sizing in pseudo-polynomial time. ISPD (2003)