A Test Partitioning Technique for Scheduling Tests for Thermally Constrained 3D Integrated Circuits.
Spencer K. MillicanKewal K. SalujaPublished in: VLSI Design (2014)
Keyphrases
- integrated circuit
- statistical tests
- built in self test
- test cases
- test generation
- test data
- test suite
- scheduling algorithm
- resource allocation
- post hoc
- infrared
- null hypothesis
- scheduling problem
- hypothesis testing
- multiple choice
- item response theory
- real time database systems
- resource constraints
- printed circuit boards
- information systems
- signal processing
- round robin
- partitioning algorithm
- statistically significant
- low cost
- diagnostic tests
- np hard