Senling Wang

Publication Activity (10 Years)

Years Active: 2011-2024
Publications (10 Years): 22

Top Topics

Fault Detection

Test Generation

Random Number Generator

Top Venues

IEICE Trans. Inf. Syst.

ACM Trans. Design Autom. Electr. Syst.

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Xihong Zhou, Senling Wang, Yoshinobu Higami, Hiroshi Takahashi
Testing and Delay-Monitoring for the High Reliability of Memory-Based Programmable Logic Device. IEICE Trans. Inf. Syst. 107 (1) (2024)
Qingsong Peng, Jingchang Bian, Zhengfeng Huang, Senling Wang, Aibin Yan
A Compact TRNG Design for FPGA Based on the Metastability of RO-driven Shift Registers. ACM Trans. Design Autom. Electr. Syst. 29 (1) (2024)
Senling Wang, Xihong Zhou, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima
Test Point Insertion for Multi-Cycle Power-On Self-Test. ACM Trans. Design Autom. Electr. Syst. 28 (3) (2023)
Tianming Ni, Fei Li, Qingsong Peng, Senling Wang, Xiaoqing Wen
A Lightweight and Machine-Learning-Resistant PUF framework based on Nonlinear Structure and Obfuscating Challenges. AsianHOST (2023)
Naoya Tahara, Senling Wang, Hiroshi Kai, Hiroshi Takahashi, Masakatu Morii
QR-Code with Superimposed Text. APNOMS (2023)
Mu Nie, Wen Jiang, Wankou Yang, Senling Wang, Xiaoqing Wen, Tianming Ni
Enhancing Defect Diagnosis and Localization in Wafer Map Testing Through Weakly Supervised Learning. ATS (2023)
Senling Wang, Shaoqi Wei, Jun Ma, Hiroshi Kai, Yoshinobu Higami, Hiroshi Takahashi, Akihiro Shimizu, Xiaoqing Wen, Tianming Ni
SASL-JTAG: A Light-Weight Dependable JTAG. DFT (2023)
Tianming Ni, Qingsong Peng, Jingchang Bian, Liang Yao, Zhengfeng Huang, Aibin Yan, Senling Wang, Xiaoqing Wen
Design of True Random Number Generator Based on Multi-Ring Convergence Oscillator Using Short Pulse Enhanced Randomness. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (12) (2023)
Tsutomu Inamoto, Tomoki Nishino, Senling Wang, Yoshinobu Higami, Hiroshi Takahashi
Preliminary Study on Noise-Resilient Artificial Neural Networks for On-Chip Test Generation. GCCE (2022)
Hanan T. Al-Awadhi, Tomoki Aono, Senling Wang, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima
FF-Control Point Insertion (FF-CPI) to Overcome the Degradation of Fault Detection under Multi-Cycle Test for POST. IEICE Trans. Inf. Syst. (11) (2020)
Takaaki Kato, Senling Wang, Yasuo Sato, Seiji Kajihara, Xiaoqing Wen
A Flexible Scan-in Power Control Method in Logic BIST and Its Evaluation with TEG Chips. IEEE Trans. Emerg. Top. Comput. 8 (3) (2020)
Senling Wang, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Jun Matsushima
Automotive Functional Safety Assurance by POST with Sequential Observation. IEEE Des. Test 35 (3) (2018)
Shigeyuki Oshima, Takaaki Kato, Senling Wang, Yasuo Sato, Seiji Kajihara
On Flip-Flop Selection for Multi-cycle Scan Test with Partial Observation in Logic BIST. ATS (2018)
Senling Wang, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima
Fault-detection-strengthened method to enable the POST for very-large automotive MCU in compliance with ISO26262. ETS (2018)
Senling Wang, Tomoki Aono, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima
Capture-Pattern-Control to Address the Fault Detection Degradation Problem of Multi-cycle Test in Logic BIST. ATS (2018)
Yoshinobu Higami, Senling Wang, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja
A Method for Diagnosing Bridging Fault between a Gate Signal Line and a Clock Line. IEICE Trans. Inf. Syst. (9) (2017)
Senling Wang, Yoshinobu Higami, Hiroshi Takahashi, Masayuki Sato, Mitsunori Katsu, Shoichi Sekiguchi
Testing of Interconnect Defects in Memory Based Reconfigurable Logic Device (MRLD). ATS (2017)
Yoshinobu Higami, Senling Wang, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja
Diagnosis Methods for Gate Delay Faults with Various Amounts of Delays. IPSJ Trans. Syst. LSI Des. Methodol. 9 (2016)
Takaaki Kato, Senling Wang, Yasuo Sato, Seiji Kajihara, Xiaoqing Wen
A Flexible Power Control Method for Right Power Testing of Scan-Based Logic BIST. ATS (2016)
Senling Wang, Hanan T. Al-Awadhi, Soh Hamada, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Jun Matsushima
Structure-Based Methods for Selecting Fault-Detection-Strengthened FF under Multi-cycle Test with Sequential Observation. ATS (2016)
Senling Wang, Yasuo Sato, Seiji Kajihara, Hiroshi Takahashi
Physical Power Evaluation of Low Power Logic-BIST Scheme Using Test Element Group Chip. J. Low Power Electron. 11 (4) (2015)
Yoshinobu Higami, Senling Wang, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja
Diagnosis of Delay Faults Considering Hazards. ISVLSI (2015)
Senling Wang, Yasuo Sato, Seiji Kajihara, Kohei Miyase
Scan-Out Power Reduction for Logic BIST. IEICE Trans. Inf. Syst. (9) (2013)
Yasuo Sato, Senling Wang, Takaaki Kato, Kohei Miyase, Seiji Kajihara
Low Power BIST for Scan-Shift and Capture Power. Asian Test Symposium (2012)
Senling Wang, Yasuo Sato, Kohei Miyase, Seiji Kajihara
A Scan-Out Power Reduction Method for Multi-cycle BIST. Asian Test Symposium (2012)
Xiaoxin Fan, Sudhakar M. Reddy, Senling Wang, Seiji Kajihara, Yasuo Sato
Genetic algorithm based approach for segmented testing. DSN Workshops (2011)