Jun Matsushima

Publication Activity (10 Years)

Years Active: 2008-2023
Publications (10 Years): 13

Top Topics

Reduction Method

Tennessee Eastman

Fault Detection

Hardware Software Co Design

Top Venues

IEICE Trans. Inf. Syst.

Publications

Senling Wang, Xihong Zhou, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima
Test Point Insertion for Multi-Cycle Power-On Self-Test. ACM Trans. Design Autom. Electr. Syst. 28 (3) (2023)
Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima, Oussama Laouamri, Naveen Khanna, Jeff Mayer, Nilanjan Mukherjee
A New Framework for RTL Test Points Insertion Facilitating a "Shift-Left DFT" Strategy. ITC (2023)
Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima
A Power Reduction Method for Scan Testing in Ultra-Low Power Designs. ATS (2021)
Hanan T. Al-Awadhi, Tomoki Aono, Senling Wang, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima
FF-Control Point Insertion (FF-CPI) to Overcome the Degradation of Fault Detection under Multi-Cycle Test for POST. IEICE Trans. Inf. Syst. (11) (2020)
Senling Wang, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Jun Matsushima
Automotive Functional Safety Assurance by POST with Sequential Observation. IEEE Des. Test 35 (3) (2018)
Koji Asami, Yoshiro Tamura, Haruo Kobayashi, Jun Matsushima, Yoichi Maeda, Kazumi Hatayama
Innovative practices on test in Japan. VTS (2018)
Senling Wang, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima
Fault-detection-strengthened method to enable the POST for very-large automotive MCU in compliance with ISO26262. ETS (2018)
Senling Wang, Tomoki Aono, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima
Capture-Pattern-Control to Address the Fault Detection Degradation Problem of Multi-cycle Test in Logic BIST. ATS (2018)
Yoichi Maeda, Jun Matsushima, Ron Press
Automotive IC On-line Test Techniques and the Application of Deterministic ATPG-Based Runtime Test. ATS (2017)
Shinichi Shibahara, Chikafumi Takahashi, Kazuki Fukuoka, Yuko Kitaji, Takahiro Irita, Hirotaka Hara, Yasuhisa Shimazaki, Jun Matsushima
A 16 nm FinFET Heterogeneous Nona-Core SoC Supporting ISO26262 ASIL B Standard. IEEE J. Solid State Circuits 52 (1) (2017)
Hiroyuki Iwata, Jun Matsushima
Multi-configuration Scan Structure for Various Purposes. ATS (2016)
Senling Wang, Hanan T. Al-Awadhi, Soh Hamada, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Jun Matsushima
Structure-Based Methods for Selecting Fault-Detection-Strengthened FF under Multi-cycle Test with Sequential Observation. ATS (2016)
Chikafumi Takahashi, Shinichi Shibahara, Kazuki Fukuoka, Jun Matsushima, Yuko Kitaji, Yasuhisa Shimazaki, Hirotaka Hara, Takahiro Irita
4.5 A 16nm FinFET heterogeneous nona-core SoC complying with ISO26262 ASIL-B: Achieving 10-7 random hardware failures per hour reliability. ISSCC (2016)
Masanori Kurimoto, Jun Matsushima, Shigeki Ohbayashi, Yoshiaki Fukui, Michio Komoda, Nobuhiro Tsuda
A Yield and Reliability Improvement Methodology Based on Logic Redundant Repair with a Repairable Scan Flip-Flop Designed by Push Rule. ACM Trans. Design Autom. Electr. Syst. 17 (2) (2012)
Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima, Masahiro Takakura
An Effective At-Speed Scan Testing Approach Using Multiple-Timing Clock Waveforms. Asian Test Symposium (2012)
Masanori Kurimoto, Jun Matsushima, Shigeki Ohbayashi, Yoshiaki Fukui
A yield improvement methodology based on logic redundant repair with a repairable scan flip-flop designed by push rule. ISQED (2010)
Jun Matsushima, Yoichi Maeda, Masahiro Takakura
CooLBIST: An Effective Approach of Test Power Reduction for LBIST. ATS (2008)