4.5 A 16nm FinFET heterogeneous nona-core SoC complying with ISO26262 ASIL-B: Achieving 10-7 random hardware failures per hour reliability.
Chikafumi TakahashiShinichi ShibaharaKazuki FukuokaJun MatsushimaYuko KitajiYasuhisa ShimazakiHirotaka HaraTakahiro IritaPublished in: ISSCC (2016)
Keyphrases
- hardware and software
- embedded systems
- low cost
- failure rate
- hardware software co design
- real time
- low power
- computer systems
- computing systems
- hardware architecture
- random number generator
- massively parallel
- error detection
- reliability analysis
- root cause
- hardware software partitioning
- commit protocols
- heterogeneous computing
- heterogeneous systems
- parallel architectures
- hardware design
- computing power
- data acquisition
- infrared
- data management
- neural network