Physical Power Evaluation of Low Power Logic-BIST Scheme Using Test Element Group Chip.
Senling WangYasuo SatoSeiji KajiharaHiroshi TakahashiPublished in: J. Low Power Electron. (2015)
Keyphrases
- low power
- built in self test
- power consumption
- high power
- high speed
- low cost
- single chip
- power dissipation
- integrated circuit
- chip design
- logic circuits
- ultra low power
- low power consumption
- mixed signal
- power management
- cmos technology
- power reduction
- energy efficiency
- power saving
- vlsi circuits
- wireless transmission
- vlsi architecture
- delay insensitive
- signal processor
- gate array
- energy saving
- real time
- digital signal processing
- energy dissipation
- image sensor
- multi channel