Soft error reduction through gate input dependent weighted sizing in combinational circuits.
Warin SootkaneungKewal K. SalujaPublished in: ISQED (2011)
Keyphrases
- error reduction
- classification error
- multiple input
- semi supervised
- asynchronous circuits
- significant improvement
- classification accuracy
- logic circuits
- iterative learning
- input data
- dimensionality reduction
- decision rules
- semi supervised learning
- cmos technology
- machine learning
- supervised learning
- feature selection