Kyuchull Kim

Publication Activity (10 Years)

Years Active: 1990-2009
Publications (10 Years): 0

Publications

Kyuchull Kim, Kewal K. Saluja
Low-Area Wrapper Cell Design for Hierarchical SoC Testing. J. Electron. Test. 25 (6) (2009)
Kyuchull Kim, Kewal K. Saluja
HYSIM: Hybrid Fault Simulation for Synchronous Sequential Circuits. VLSI Design 4 (3) (1996)
Manoj Franklin, Kewal K. Saluja, Kyuchull Kim
Fast computation of MISR signatures. VLSI Design (1995)
Kyuchull Kim, Kewal K. Saluja
CCSTG: an efficient test pattern generator for sequential circuits. VTS (1993)
Kyuchull Kim, Kewal K. Saluja
On fault deletion problem in concurrent fault simulation for synchronous sequential circuits. VTS (1992)
Kewal K. Saluja, Kyuchull Kim
Improved Test Generation for High-Activity Circuits. IEEE Des. Test Comput. 7 (4) (1990)