Hui Guo

Publication Activity (10 Years)

Years Active: 1997-2024
Publications (10 Years): 8

Top Topics

Embedded Systems

Top Venues

Publications

Sajid Hussain, Hui Guo, Tuo Li, Sri Parameswaran
MP-ORAM: A Novel ORAM Design for Multicore Processor Systems. IEEE Trans. Dependable Secur. Comput. 21 (4) (2024)
Sajid Hussain, Hui Guo, Tuo Li, Hassaan Saadat, Sri Parameswaran
COPS: A complete oblivious processing system. Microprocess. Microsystems 85 (2021)
Mubashir Hussain, Amin Malekpour, Hui Guo, Sri Parameswaran
EETD: An Energy Efficient Design for Runtime Hardware Trojan Detection in Untrusted Network-on-Chip. ISVLSI (2018)
Mubashir Hussain, Hui Guo
A Bandwidth-Aware Authentication Scheme for Packet-Integrity Attack Detection on Trojan Infected NoC. VLSI-SoC (2018)
Tao Liu, Hui Guo, Sri Parameswaran, Xiaobo Sharon Hu
iCETD: An improved tag generation design for memory data authentication in embedded processor systems. Integr. 56 (2017)
Mubashir Hussain, Hui Guo
Packet Leak Detection on Hardware-Trojan Infected NoCs for MPSoC Systems. ICCSP (2017)
Tao Liu, Hui Guo, Sri Parameswaran, Xiaobo Sharon Hu
Improving tag generation for memory data authentication in embedded processor systems. ASP-DAC (2016)
Mahanama Wickramasinghe, Hui Guo
Data-Space Relocation to Improve Data Cache Performance for Embedded Multi-threaded Processor Systems. ICNCC (2016)
Ji Gu, Hui Guo, Tohru Ishihara
DLIC: Decoded loop instructions caching for energy-aware embedded processors. ACM Trans. Embed. Comput. Syst. 13 (1) (2013)
Mei Hong, Hui Guo, Sri Parameswaran
Dynamic encryption key design and management for memory data encryption in embedded systems. ISVLSI (2013)
Ji Gu, Hui Guo
Reducing Power and Energy Overhead in Instruction Prefetching for Embedded Processor Systems. Int. J. Handheld Comput. Res. 2 (4) (2011)
Ji Gu, Hui Guo, Patrick Li
An on-chip instruction cache design with one-bit tag for low-power embedded systems. Microprocess. Microsystems 35 (4) (2011)
Ji Gu, Hui Guo
Enabling large decoded instruction loop caching for energy-aware embedded processors. CASES (2010)
Hui Guo, Sri Parameswaran
Shifted gray encoding to reduce instruction memory address bus switching for low-power embedded systems. J. Syst. Archit. 56 (4-6) (2010)
Ji Gu, Hui Guo
An Energy Efficient Instruction Prefetching Scheme for Embedded Processors. UCMA (2010)
Ji Gu, Hui Guo
An Efficient Segmental Bus-Invert Coding Method for Instruction Memory Data Bus Switching Reduction. EURASIP J. Embed. Syst. 2009 (2009)
Swarnalatha Radhakrishnan, Hui Guo, Sri Parameswaran, Aleksandar Ignjatovic
HMP-ASIPs: heterogeneous multi-pipeline application-specific instruction-set processors. IET Comput. Digit. Tech. 3 (1) (2009)
Ji Gu, Hui Guo
A Segmental Bus-invert Coding Method for Instruction Memory Data Bus Power Efficiency. ISCAS (2009)
Ji Gu, Hui Guo, Patrick Li
ROBTIC: An On-chip Instruction Cache Design for Low Power Embedded Systems. RTCSA (2009)
Swarnalatha Radhakrishnan, Hui Guo, Sri Parameswaran
Customization of application specific heterogeneous multi-pipeline processors. DATE (2006)
Swarnalatha Radhakrishnan, Hui Guo, Sri Parameswaran, Aleksandar Ignjatovic
Application specific forwarding network and instruction encoding for multi-pipe ASIPs. CODES+ISSS (2006)
Hui Guo, Sri Parameswaran
Balancing System Level Pipelines with Stage Voltage Scaling. ISVLSI (2005)
Swarnalatha Radhakrishnan, Hui Guo, Sri Parameswaran
Dual-pipeline heterogeneous ASIP design. CODES+ISSS (2004)
Sri Parameswaran, Hui Guo
Power Reduction in Pipelines. ASP-DAC (1998)
Hui Guo, Sri Parameswaran
Unrolling Loops With Indeterminate Loop Counts in System Level Pipelines. ASP-DAC (1998)
Sri Parameswaran, Hui Guo
Power consumption in CMOS combinational logic blocks at high frequencies. ASP-DAC (1997)