Rakesh Chadha

Publication Activity (10 Years)

Years Active: 1987-1999
Publications (10 Years): 0

Publications

Lun Ye, Foong-Charn Chang, Peter Feldmann, Rakesh Chadha, Nagaraj Ns, Frank Cano
Chip-Level Verification for Parasitic Coupling Effects in Deep-Submicron Digital Designs. DATE (1999)
Tom Chanak, Rakesh Chadha, Kishore Singhal
Switched-capacitor simulation models for full-chips verification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11 (11) (1992)
Rakesh Chadha, Chandramouli Visweswariah, Chin-Fu Chen
-a multilevel mixed-mode mixed A/D simulator. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11 (5) (1992)
Rakesh Chadha, Chin-Fu Chen
Extension of a transistor level digital timing simulator to include first order analog behavior. ICCD (1988)
Rakesh Chadha, Chin-Fu Chen
-a multilevel mixed-mode mixed D/A simulator. ICCAD (1988)
Chandramouli Visweswariah, Rakesh Chadha, Chin-Fu Chen
Model Development and Verification for High Level Analog Blocks. DAC (1988)
Rakesh Chadha, Kishore Singhal, Jirí Vlach, Ernst Christen, Milan Vlach
WATOPT -- An Optimizer for Circuit Applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 6 (3) (1987)