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Chip-Level Verification for Parasitic Coupling Effects in Deep-Submicron Digital Designs.
Lun Ye
Foong-Charn Chang
Peter Feldmann
Rakesh Chadha
Nagaraj Ns
Frank Cano
Published in:
DATE (1999)
Keyphrases
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design space
mixed signal
low power
high speed
multi channel
functional verification
vlsi circuits
model checking
circuit design
levels of abstraction
data sets
cmos image sensor