Chip-Planning, Placement, and Global Routing of Macro/Custom Cell Integrated Circuits Using Simulated Annealing.
Carl SechenPublished in: DAC (1988)
Keyphrases
- integrated circuit
- simulated annealing
- printed circuit boards
- built in self test
- metal oxide semiconductor
- high speed
- genetic algorithm
- domain specific
- low cost
- planning problems
- metaheuristic
- tabu search
- domain independent
- high density
- simulated annealing algorithm
- chip design
- routing problem
- electron beam
- neural network
- network topology
- hill climbing
- planning domains
- evolutionary algorithm