Chip-level area routing.

Le-Chin Eugene Liu Hsiao-Ping Tseng Carl Sechen

Published in: ISPD (1998)

Keyphrases

low cost
high speed
higher level
database
neural network
routing algorithm
ad hoc networks
analog vlsi
wireless ad hoc networks
power consumption
input output
routing protocol
evolutionary algorithm
high level
learning algorithm
data sets
real time