Michael D. Hutton

Publication Activity (10 Years)

Years Active: 1991-2007
Publications (10 Years): 0

Publications

Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Michael D. Hutton, Truman Collins, Sridhar Srinivasan, Nan-Chi Chou, Peter Suaris, Chung-Kuan Cheng
Efficient Timing Analysis With Known False Paths Using Biclique Covering. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (5) (2007)
Michael D. Hutton, Richard Yuan, Jay Schleicher, Gregg Baeckler, Sammy Cheung, Kar Keng Chua, Hee Kong Phoo
A methodology for FPGA to structured-ASIC synthesis and verification. DATE Designers' Forum (2006)
Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Chung-Kuan Cheng, Michael D. Hutton
Efficient static timing analysis using a unified framework for false paths and multi-cycle paths. ASP-DAC (2006)
Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Chung-Kuan Cheng, Michael D. Hutton, Truman Collins, Sridhar Srinivasan, Nan-Chi Chou, Peter Suaris
Improving the efficiency of static timing analysis with false paths. ICCAD (2005)
Michael D. Hutton, Jay Schleicher, David M. Lewis, Bruce Pedersen, Richard Yuan, Sinan Kaptanoglu, Gregg Baeckler, Boris Ratchev, Ketan Padalia, Mark Bourgeault, Andy Lee, Henry Kim, Rahul Saini
Improving FPGA Performance and Area Using an Adaptive Logic Module. FPL (2004)
Michael D. Hutton, Jonathan Rose, Derek G. Corneil
Automatic generation of synthetic sequential benchmark circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21 (8) (2002)
Michael D. Hutton, Vinson Chan, Peter Kazarian, Victor Maruri, Tony Ngai, Jim Park, Rakesh H. Patel, Bruce Pedersen, Jay Schleicher, Sergey Y. Shumarayev
Interconnect enhancements for a high-speed PLD architecture. FPGA (2002)
Michael D. Hutton
Interconnect prediction for programmable logic devices. SLIP (2001)
Michael D. Hutton, Jonathan Rose
Applications of clone circuits to issues in physical-design. ISCAS (6) (1999)
Michael D. Hutton, Jonathan Rose
Equivalence classes of clone circuits for physical-design benchmarking. ISCAS (6) (1999)
Michael D. Hutton, Jonathan Rose, Jerry P. Grossman, Derek G. Corneil
Characterization and parameterized generation of synthetic combinational benchmark circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17 (10) (1998)
Michael D. Hutton, Jonathan Rose, Derek G. Corneil
Generation of Synthetic Sequential Benchmark Circuits. FPGA (1997)
Michael D. Hutton, Anna Lubiw
Upward Planning of Single-Source Acyclic Digraphs. SIAM J. Comput. 25 (2) (1996)
Michael D. Hutton, Jerry P. Grossman, Jonathan Rose, Derek G. Corneil
Characterization and Parameterized Random Generation of Digital Circuits. DAC (1996)
Michael D. Hutton, Anna Lubiw
Upward Planar Drawing of Single Source Acyclic Digraphs. SODA (1991)
Michael D. Hutton, Anna Lubiw
Upward Planar Drawing of Single Source Acyclic Digraphs. Planar Graphs (1991)