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Interconnect enhancements for a high-speed PLD architecture.
Michael D. Hutton
Vinson Chan
Peter Kazarian
Victor Maruri
Tony Ngai
Jim Park
Rakesh H. Patel
Bruce Pedersen
Jay Schleicher
Sergey Y. Shumarayev
Published in:
FPGA (2002)
Keyphrases
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high speed
real time
low power
management system
high speed networks
image processing
network architecture
data sets
machine learning
genetic algorithm
distributed systems
software architecture
end to end
reference model
loosely coupled
content addressable memory