Nan-Chi Chou

Publication Activity (10 Years)

Years Active: 1992-2011
Publications (10 Years): 0

Publications

Renshen Wang, Yulei Zhang, Nan-Chi Chou, Evangeline F. Y. Young, Chung-Kuan Cheng, Ronald L. Graham
Bus Matrix Synthesis Based on Steiner Graphs for Power Efficient System-on-Chip Communications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30 (2) (2011)
Renshen Wang, Nan-Chi Chou, Bill Salefski, Chung-Kuan Cheng
Low power gated bus synthesis using shortest-path Steiner graph for system-on-chip communications. DAC (2009)
Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Michael D. Hutton, Truman Collins, Sridhar Srinivasan, Nan-Chi Chou, Peter Suaris, Chung-Kuan Cheng
Efficient Timing Analysis With Known False Paths Using Biclique Covering. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (5) (2007)
Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Chung-Kuan Cheng, Michael D. Hutton, Truman Collins, Sridhar Srinivasan, Nan-Chi Chou, Peter Suaris
Improving the efficiency of static timing analysis with false paths. ICCAD (2005)
Bo Yao, Hongyu Chen, Chung-Kuan Cheng, Nan-Chi Chou, Lung-Tien Liu, Peter Suaris
Unified quadratic programming approach for mixed mode placement. ISPD (2005)
Peter Suaris, Dongsheng Wang, Nan-Chi Chou
A practical cut-based physical retiming algorithm for field programmable gate arrays. ASP-DAC (2005)
Yuzheng Ding, Peter Suaris, Nan-Chi Chou
The effect of post-layout pin permutation on timing. FPGA (2005)
Jianhua Liu, Michael Chang, Chung-Kuan Cheng, John F. MacDonald, Nan-Chi Chou, Peter Suaris
Fast adders in modern FPGAs. FPGA (2004)
Peter Suaris, Lung-Tien Liu, Yuzheng Ding, Nan-Chi Chou
Incremental physical resynthesis for timing optimization. FPGA (2004)
Dongsheng Wang, Peter Suaris, Nan-Chi Chou
A Practical ASIC Methdology for Flexible Clock Tree Synthesis with Routing Blockages. PATMOS (2003)
Peter Suaris, Dongsheng Wang, Pei-Ning Guo, Nan-Chi Chou
A physical retiming algorithm for field programmable gate arrays. FPGA (2003)
Hongyu Chen, Chung-Kuan Cheng, Nan-Chi Chou, Andrew B. Kahng, John F. MacDonald, Peter Suaris, Bo Yao, Zhengyong Zhu
An algebraic multigrid solver for analytical placement with layout based clustering. DAC (2003)
Nan-Chi Chou, Chung-Kuan Cheng
On general zero-skew clock net construction. IEEE Trans. Very Large Scale Integr. Syst. 3 (1) (1995)
Nan-Chi Chou, Lung-Tien Liu, Chung-Kuan Cheng, Wei-Jin Dai, Rodney Lindelof
Local ratio cut and set covering partitioning for huge logic emulation systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14 (9) (1995)
So-Zen Yao, Nan-Chi Chou, Chung-Kuan Cheng, T. C. Hu
A multi-probe approach for MCM substrate testing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13 (1) (1994)
Nan-Chi Chou, Lung-Tien Liu, Chung-Kuan Cheng, Wei-Jin Dai, Rodney Lindelof
Circuit Partitioning for Huge Logic Emulation Systems. DAC (1994)
Lung-Tien Liu, Minshine Shih, Nan-Chi Chou, Chung-Kuan Cheng, Walter H. Ku
Performance-driven partitioning using retiming and replication. ICCAD (1993)
So-Zen Yao, Nan-Chi Chou, Chung-Kuan Cheng, T. C. Hu
An optimal probe testing algorithm for the connectivity verification of MCM substrates. ICCAD (1992)