Safeen Huda

Publication Activity (10 Years)

Years Active: 2009-2024
Publications (10 Years): 10

Top Topics

Power Reduction

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Yazhou Zu, Alireza Ghaffarkhah, Hoang-Vu Dang, Brian Towles, Steven Hand, Safeen Huda, Adekunle Bello, Alexander Kolbasov, Arash Rezaei, Dayou Du, Steve Lacy, Hang Wang, Aaron Wisner, Chris Lewis, Henri Bahini
Resiliency at Scale: Managing Google's TPUv4 Machine Learning Supercomputer. NSDI (2024)
Yash Akhauri, Ahmed F. AbouElhamayed, Jordan Dotzel, Zhiru Zhang, Alexander M. Rush, Safeen Huda, Mohamed S. Abdelfattah
ShadowLLM: Predictor-based Contextual Sparsity for Large Language Models. CoRR (2024)
Dan Zhang, Safeen Huda, Ebrahim M. Songhori, Kartik Prabhu, Quoc V. Le, Anna Goldie, Azalia Mirhoseini
A full-stack search technique for domain optimized deep learning accelerators. ASPLOS (2022)
Paras Jain, Safeen Huda, Martin Maas, Joseph E. Gonzalez, Ion Stoica, Azalia Mirhoseini
Learning to Design Accurate Deep Learning Accelerators with Inaccurate Multipliers. DATE (2022)
Dan Zhang, Safeen Huda, Ebrahim M. Songhori, Quoc V. Le, Anna Goldie, Azalia Mirhoseini
A Full-stack Accelerator Search Technique for Vision Applications. CoRR (2021)
Kevin E. Murray, Jason Luu, Matthew J. P. Walker, Conor McCullough, Sen Wang, Safeen Huda, Bo Yan, Charles Chiasson, Kenneth B. Kent, Jason Helge Anderson, Jonathan Rose, Vaughn Betz
Optimizing FPGA Logic Block Architectures for Arithmetic. IEEE Trans. Very Large Scale Integr. Syst. 28 (6) (2020)
Safeen Huda, Jason Helge Anderson
Leveraging Unused Resources for Energy Optimization of FPGA Interconnect. IEEE Trans. Very Large Scale Integr. Syst. 25 (8) (2017)
Safeen Huda, Jason Helge Anderson
Towards PVT-Tolerant Glitch-Free Operation in FPGAs. FPGA (2016)
S. Alexander Chin, Jason Luu, Safeen Huda, Jason Helge Anderson
Hybrid LUT/Multiplexer FPGA Logic Architectures. IEEE Trans. Very Large Scale Integr. Syst. 24 (4) (2016)
Safeen Huda, Jason Helge Anderson
Power Optimization of FPGA Interconnect Via Circuit and CAD Techniques. ISPD (2016)
Safeen Huda, Jason Helge Anderson, Hirotaka Tamura
Optimizing effective interconnect capacitance for FPGA power reduction. FPGA (2014)
Jason Luu, Conor McCullough, Sen Wang, Safeen Huda, Bo Yan, Charles Chiasson, Kenneth B. Kent, Jason Helge Anderson, Jonathan Rose, Vaughn Betz
On Hard Adders and Carry Chains in FPGAs. FCCM (2014)
Aynaz Vatankhahghadim, Safeen Huda, Ali Sheikholeslami
A Survey on Circuit Modeling of Spin-Transfer-Torque Magnetic Tunnel Junctions. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2014)
Safeen Huda, Jason Helge Anderson, Hirotaka Tamura
Charge recycling for power reduction in FPGA interconnect. FPL (2013)
Safeen Huda, Ali Sheikholeslami
A Novel STT-MRAM Cell With Disturbance-Free Read Operation. IEEE Trans. Circuits Syst. I Regul. Pap. (6) (2013)
David Halupka, Safeen Huda, William Song, Ali Sheikholeslami, Koji Tsunoda, Chikako Yoshida, Masaki Aoki
Negative-resistance read and write schemes for STT-MRAM in 0.13µm CMOS. ISSCC (2010)
Safeen Huda, Muntasir Mallick, Jason Helge Anderson
Clock gating architectures for FPGA power reduction. FPL (2009)