Yazhou Zu

Publication Activity (10 Years)

Years Active: 2013-2024
Publications (10 Years): 12

Top Topics

Predictive Modeling

Power Management

Design Space Exploration

Spatial And Temporal

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

Yazhou Zu, Alireza Ghaffarkhah, Hoang-Vu Dang, Brian Towles, Steven Hand, Safeen Huda, Adekunle Bello, Alexander Kolbasov, Arash Rezaei, Dayou Du, Steve Lacy, Hang Wang, Aaron Wisner, Chris Lewis, Henri Bahini
Resiliency at Scale: Managing Google's TPUv4 Machine Learning Supercomputer. NSDI (2024)
Jingwen Leng, Alper Buyuktosunoglu, Ramon Bertran, Pradip Bose, Yazhou Zu, Vijay Janapa Reddi
Predictive Guardbanding: Program-Driven Timing Margin Reduction for GPUs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40 (1) (2021)
Jingwen Leng, Alper Buyuktosunoglu, Ramon Bertran, Pradip Bose, Yazhou Zu, Vijay Janapa Reddi
Erratum to "Predictive Guardbanding: Program-Driven Timing Margin Reduction for GPUs". IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40 (6) (2021)
Sameer Kumar, James Bradbury, Cliff Young, Yu Emma Wang, Anselm Levskaya, Blake A. Hechtman, Dehao Chen, HyoukJoong Lee, Mehmet Deveci, Naveen Kumar, Pankaj Kanwar, Shibo Wang, Skye Wanderman-Milne, Steve Lacy, Tao Wang, Tayo Oguntebi, Yazhou Zu, Yuanzhong Xu, Andy Swing
Exploring the limits of Concurrency in ML Training on Google TPUs. CoRR (2020)
An Zou, Jingwen Leng, Xin He, Yazhou Zu, Christopher D. Gill, Vijay Janapa Reddi, Xuan Zhang
Voltage-Stacked Power Delivery Systems: Reliability, Efficiency, and Power Management. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (12) (2020)
Yazhou Zu, Daniel Richins, Charles Lefurgy, Vijay Janapa Reddi
Fine-Tuning the Active Timing Margin (ATM) Control Loop for Maximizing Multi-core Efficiency on an IBM POWER Server. HPCA (2019)
An Zou, Jingwen Leng, Xin He, Yazhou Zu, Christopher D. Gill, Vijay Janapa Reddi, Xuan Zhang
Voltage-Stacked GPUs: A Control Theory Driven Cross-Layer Solution for Practical Voltage Stacking in GPUs. MICRO (2018)
An Zou, Jingwen Leng, Xin He, Yazhou Zu, Vijay Janapa Reddi, Xuan Zhang
Efficient and reliable power delivery in voltage-stacked manycore system with hybrid charge-recycling regulators. DAC (2018)
Yazhou Zu, Wei Huang, Indrani Paul, Vijay Janapa Reddi
Ti-States: Power Management in Active Timing Margin Processors. IEEE Micro 37 (3) (2017)
Hasan Genc, Yazhou Zu, Ting-Wu Chin, Matthew Halpern, Vijay Janapa Reddi
Flying IoT: Toward Low-Power Vision in the Sky. IEEE Micro 37 (6) (2017)
An Zou, Jingwen Leng, Yazhou Zu, Tao Tong, Vijay Janapa Reddi, David M. Brooks, Gu-Yeon Wei, Xuan Zhang
Ivory: Early-Stage Design Space Exploration Tool for Integrated Voltage Regulators. DAC (2017)
Yazhou Zu, Wei Huang, Indrani Paul, Vijay Janapa Reddi
Ti-states: Processor power management in the temperature inversion region. MICRO (2016)
Jingwen Leng, Yazhou Zu, Vijay Janapa Reddi
GPU voltage noise: Characterization and hierarchical smoothing of spatial and temporal voltage noise interference in GPU architectures. HPCA (2015)
Yazhou Zu, Charles R. Lefurgy, Jingwen Leng, Matthew Halpern, Michael S. Floyd, Vijay Janapa Reddi
Adaptive guardband scheduling to improve system-level efficiency of the POWER7+. MICRO (2015)
Jingwen Leng, Yazhou Zu, Minsoo Rhu, Meeta Sharma Gupta, Vijay Janapa Reddi
GPUVolt: modeling and characterizing voltage noise in GPU architectures. ISLPED (2014)
Yazhou Zu, Tian Huang, Yongxin Zhu
An Efficient Power-Aware Resource Scheduling Strategy in Virtualized Datacenters. ICPADS (2013)