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Clock gating architectures for FPGA power reduction.

Safeen HudaMuntasir MallickJason Helge Anderson
Published in: FPL (2009)
Keyphrases
  • power reduction
  • power consumption
  • clock gating
  • low power
  • power saving
  • energy efficiency
  • multithreading
  • high speed
  • low cost
  • power dissipation
  • pattern recognition
  • wireless sensor networks