Yu-Shen Yang

Publication Activity (10 Years)

Years Active: 2003-2014
Publications (10 Years): 0

Top Topics

Failure Prediction

Simulation Tools

Top Venues

Publications

Zissis Poulos, Yu-Shen Yang, Andreas G. Veneris, Bao Le
Simulation and satisfiability guided counter-example triage for RTL design debugging. ISQED (2014)
Zissis Poulos, Yu-Shen Yang, Andreas G. Veneris
A failure triage engine based on error trace signature extraction. IOLTS (2013)
Zissis Poulos, Yu-Shen Yang, Jason Helge Anderson, Andreas G. Veneris, Bao Le
Leveraging reconfigurability to raise productivity in FPGA functional debug. DATE (2012)
Yu-Shen Yang, Andreas G. Veneris, Nicola Nicolici, Masahiro Fujita
Automated data analysis techniques for a modern silicon debug environment. ASP-DAC (2012)
Yu-Shen Yang, Andreas G. Veneris, Nicola Nicolici
Automating Data Analysis and Acquisition Setup in a Silicon Debug Environment. IEEE Trans. Very Large Scale Integr. Syst. 20 (6) (2012)
Yu-Shen Yang, Subarna Sinha, Andreas G. Veneris, Robert K. Brayton
Automating Logic Transformations With Approximate SPFDs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30 (5) (2011)
Yu-Shen Yang, Brian Keng, Nicola Nicolici, Andreas G. Veneris, Sean Safarpour
Automated silicon debug data analysis techniques for a hardware data acquisition environment. ISQED (2010)
Yu-Shen Yang, Subarna Sinha, Andreas G. Veneris, Robert K. Brayton, Duncan Exon Smith
Sequential logic rectifications with approximate SPFDs. DATE (2009)
Yu-Shen Yang, Nicola Nicolici, Andreas G. Veneris
Automated data analysis solutions to silicon debug. DATE (2009)
Sobeeh Almukhaizim, Yiorgos Makris, Yu-Shen Yang, Andreas G. Veneris
On the Minimization of Potential Transient Errors and SER in Logic Circuits Using SPFD. IOLTS (2008)
Yu-Shen Yang, Subarnarekha Sinha, Andreas G. Veneris, Robert K. Brayton
Automating Logic Rectification by Approximate SPFDs. ASP-DAC (2007)
Sobeeh Almukhaizim, Yiorgos Makris, Yu-Shen Yang, Andreas G. Veneris
Seamless Integration of SER in Rewiring-Based Design Space Exploration. ITC (2006)
Yu-Shen Yang, Andreas G. Veneris, Paul J. Thadikaran, Srikanth Venkataraman
Extraction error modeling and automated model debugging in high-performance custom designs. IEEE Trans. Very Large Scale Integr. Syst. 14 (7) (2006)
Yu-Shen Yang, Andreas G. Veneris, Paul J. Thadikaran, Srikanth Venkataraman
Extraction Error Modeling and Automated Model Debugging in High-Performance Low Power Custom Designs. DATE (2005)
Yu-Shen Yang, Jiang Brandon Liu, Paul J. Thadikaran, Andreas G. Veneris
Extraction Error Diagnosis and Correction in High-Performance Designs. ITC (2003)
Yu-Shen Yang, Jiang Brandon Liu, Paul J. Thadikaran, Andreas G. Veneris
Extraction Error Analysis, Diagnosis and Correction in Custom-Made High-Performance Designs. MTV (2003)