Nicola Nicolici

ORCID

Publication Activity (10 Years)

Years Active: 1998-2024
Publications (10 Years): 20

Top Venues

IEEE Des. Test

IEEE Trans. Computers

ICCAD

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

Trevor E. Pogue, Nicola Nicolici
Fast Inner-Product Algorithms and Architectures for Deep Neural Network Accelerators. IEEE Trans. Computers 73 (2) (2024)
Nicola Nicolici
Interview With Janusz Rajski. IEEE Des. Test 41 (4) (2024)
Nicola Nicolici
Interview With Prof. Sung-Mo (Steve) Kang. IEEE Des. Test 40 (3) (2023)
Nicola Nicolici
Interview With Janet Olson. IEEE Des. Test 40 (1) (2023)
Trevor E. Pogue, Nicola Nicolici
Fast Inner-Product Algorithms and Architectures for Deep Neural Network Accelerators. CoRR (2023)
Trevor E. Pogue, Nicola Nicolici
Incremental Fault Analysis: Relaxing the Fault Model of Differential Fault Attacks. IEEE Trans. Very Large Scale Integr. Syst. 28 (3) (2020)
Amin Vali, Nicola Nicolici
Bit-Flip Detection-Driven Selection of Trace Signals. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (5) (2018)
Pouya Taatizadeh, Nicola Nicolici
Emulation Infrastructure for the Evaluation of Hardware Assertions for Post-Silicon Validation. IEEE Trans. Very Large Scale Integr. Syst. 25 (6) (2017)
Xiaobing Shi, Nicola Nicolici
A generic embedded sequence generator for constrained-random validation with weighted distributions. IOLTS (2017)
Pouya Taatizadeh, Nicola Nicolici
An automated SAT-based method for the design of on-chip bit-flip detectors. ICCAD (2017)
Nicola Nicolici, Haralampos-G. D. Stratigopoulos
Guest Editors' Introduction: Top Papers from the 2015 International Test Conference. IEEE Des. Test 33 (6) (2016)
Xiaobing Shi, Nicola Nicolici
On-Chip Cube-Based Constrained-Random Stimuli Generation for Post-Silicon Validation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35 (6) (2016)
Pouya Taatizadeh, Nicola Nicolici
Automated Selection of Assertions for Bit-Flip Detection During Post-Silicon Validation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35 (12) (2016)
Amin Vali, Nicola Nicolici
Bit-flip detection-driven selection of trace signals. ETS (2016)
Xiaobing Shi, Nicola Nicolici
Generating Cyclic-Random Sequences in a Constrained Space for In-System Validation. IEEE Trans. Computers 65 (12) (2016)
Amin Vali, Nicola Nicolici
Satisfiability-Based Analysis of Failing Traces during Post-silicon Debug. NATW (2015)
Xiaobing Shi, Nicola Nicolici
On-Chip Generation of Uniformly Distributed Constrained-Random Stimuli for Post-Silicon Validation. ICCAD (2015)
Pouya Taatizadeh, Nicola Nicolici
Emulation-based selection and assessment of assertion checkers for post-silicon validation. ICCD (2015)
Pouya Taatizadeh, Nicola Nicolici
A methodology for automated design of embedded bit-flips detectors in post-silicon validation. DATE (2015)
Jason Thong, Nicola Nicolici
SAT Solving using FPGA-based Heterogeneous Computing. ICCAD (2015)
Xiaobing Shi, Nicola Nicolici
On Supporting Sequential Constraints for On-Chip Generation of Post-silicon Validation Stimuli. ATS (2014)
Zahra Lak, Nicola Nicolici
A Novel Algorithmic Approach to Aid Post-Silicon Delay Measurement and Clock Tuning. IEEE Trans. Computers 63 (5) (2014)
Behzad Mahdavikhah, Ramin Mafi, Shahin Sirouspour, Nicola Nicolici
A Multiple-FPGA parallel computing architecture for real-time simulation of soft-object deformation. ACM Trans. Embed. Comput. Syst. 13 (4) (2014)
Xiaobing Shi, Nicola Nicolici
On-chip constrained random stimuli generation for post-silicon validation using compact masks. ITC (2014)
Adam B. Kinsman, Ho Fai Ko, Nicola Nicolici
Hardware-efficient on-chip generation of time-extensive constrained-random sequences for in-system validation. DAC (2013)
Phillip Kinsman, Nicola Nicolici
NoC-Based FPGA Acceleration for Monte Carlo Simulations with Applications to SPECT Imaging. IEEE Trans. Computers 62 (3) (2013)
Jason Thong, Nicola Nicolici
FPGA acceleration of enhanced boolean constraint propagation for SAT solvers. ICCAD (2013)
Nicola Nicolici
On-chip stimuli generation for post-silicon validation. HLDVT (2012)
Zahra Lak, Nicola Nicolici
On Using On-Chip Clock Tuning Elements to Address Delay Degradation Due to Circuit Aging. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31 (12) (2012)
Adam B. Kinsman, Ho Fai Ko, Nicola Nicolici
In-system constrained-random stimuli generation for post-silicon validation. ITC (2012)
Yu-Shen Yang, Andreas G. Veneris, Nicola Nicolici, Masahiro Fujita
Automated data analysis techniques for a modern silicon debug environment. ASP-DAC (2012)
Ho Fai Ko, Nicola Nicolici
Mapping Trigger Conditions onto Trigger Units during Post-silicon Validation and Debugging. IEEE Trans. Computers 61 (11) (2012)
Yu-Shen Yang, Andreas G. Veneris, Nicola Nicolici
Automating Data Analysis and Acquisition Setup in a Silicon Debug Environment. IEEE Trans. Very Large Scale Integr. Syst. 20 (6) (2012)
Adam B. Kinsman, Nicola Nicolici
A VLSI Architecture and the FPGA Prototype for MPEG-2 Audio/Video Decoding. IEEE Trans. Very Large Scale Integr. Syst. 19 (3) (2011)
Phillip Kinsman, Nicola Nicolici
Dynamic binary translation to a reconfigurable target for on-the-fly acceleration. DAC (2011)
Zahra Lak, Nicola Nicolici
In-system and on-the-fly clock tuning mechanism to combat lifetime performance degradation. ICCAD (2011)
George A. Constantinides, Adam B. Kinsman, Nicola Nicolici
Numerical Data Representations for FPGA-Based Scientific Computing. IEEE Des. Test Comput. 28 (4) (2011)
Adam B. Kinsman, Nicola Nicolici
Trade-Offs in Test Data Compression and Deterministic X-Masking of Responses. IEEE Trans. Computers 60 (4) (2011)
Ho Fai Ko, Adam B. Kinsman, Nicola Nicolici
Design-for-Debug Architecture for Distributed Embedded Logic Analysis. IEEE Trans. Very Large Scale Integr. Syst. 19 (8) (2011)
Jason Thong, Nicola Nicolici
An Optimal and Practical Approach to Single Constant Multiplication. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30 (9) (2011)
Adam B. Kinsman, Nicola Nicolici
Automated Range and Precision Bit-Width Allocation for Iterative Computations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30 (9) (2011)
Ehab Anis Daoud, Nicola Nicolici
On Using Lossy Compression for Repeatable Experiments during Silicon Debug. IEEE Trans. Computers 60 (7) (2011)
Zahra Lak, Nicola Nicolici
A New Algorithm for Post-Silicon Clock Measurement and Tuning. DFT (2011)
Ehab Anis Daoud, Nicola Nicolici
Embedded Debug Architecture for Bypassing Blocking Bugs During Post-Silicon Validation. IEEE Trans. Very Large Scale Integr. Syst. 19 (4) (2011)
Adam B. Kinsman, Nicola Nicolici
Computational Vector-Magnitude-Based Range Determination for Scientific Abstract Data Types. IEEE Trans. Computers 60 (11) (2011)
George A. Constantinides, Nicola Nicolici
Guest Editors' Introduction: Surveying the Landscape of FPGA Accelerator Research. IEEE Des. Test Comput. 28 (4) (2011)
Behzad Mahdavikhah, Ramin Mafi, Shahin Sirouspour, Nicola Nicolici
Haptic rendering of deformable objects using a multiple FPGA parallel computing architecture. FPGA (2010)
Yu-Shen Yang, Brian Keng, Nicola Nicolici, Andreas G. Veneris, Sean Safarpour
Automated silicon debug data analysis techniques for a hardware data acquisition environment. ISQED (2010)
Ramin Mafi, Shahin Sirouspour, Behzad Mahdavikhah, Brian Moody, Kaveh Elizeh, Adam B. Kinsman, Nicola Nicolici
A Parallel Computing Platform for Real-Time Haptic Interaction with Deformable Bodies. IEEE Trans. Haptics 3 (3) (2010)
Adam B. Kinsman, Nicola Nicolici
Bit-Width Allocation for Hardware Accelerators for Scientific Computing Using SAT-Modulo Theory. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (3) (2010)
Jason Thong, Nicola Nicolici
Combined optimal and heuristic approaches for multiple constant multiplication. ICCD (2010)
Kaveh Elizeh, Nicola Nicolici
Embedded memory binding in FPGAs. DAC (2010)
Adam B. Kinsman, Nicola Nicolici
Time-Multiplexed Compressed Test of SOC Designs. IEEE Trans. Very Large Scale Integr. Syst. 18 (8) (2010)
Nicola Nicolici
On improving real-time observability for in-system post-silicon debug. LATW (2010)
Ho Fai Ko, Nicola Nicolici
Combining scan and trace buffers for enhancing real-time observability in post-silicon debugging. ETS (2010)
Subhasish Mitra, Sanjit A. Seshia, Nicola Nicolici
Post-silicon validation opportunities, challenges and recent advances. DAC (2010)
Ho Fai Ko, Nicola Nicolici
Automated trace signals selection using the RTL descriptions. ITC (2010)
Adam B. Kinsman, Nicola Nicolici
Robust design methods for hardware accelerators for iterative algorithms in scientific computing. DAC (2010)
Jason Thong, Nicola Nicolici
A novel optimal single constant multiplication algorithm. DAC (2010)
Brian C. Richards, Nicola Nicolici, Henry Chen, Kevin Chao, Robert Abiad, Dan Werthimer, Borivoje Nikolic
A 1.5GS/s 4096-point digital spectrum analyzer for space-borne applications. CICC (2009)
Ho Fai Ko, Nicola Nicolici
Algorithms for State Restoration and Trace-Signal Selection for Data Acquisition in Silicon Debug. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28 (2) (2009)
Adam B. Kinsman, Nicola Nicolici
Computational bit-width allocation for operations in vector calculus. ICCD (2009)
Jason Thong, Nicola Nicolici
Time-Efficient Single Constant Multiplication Based on Overlapping Digit Patterns. IEEE Trans. Very Large Scale Integr. Syst. 17 (9) (2009)
Yu-Shen Yang, Nicola Nicolici, Andreas G. Veneris
Automated data analysis solutions to silicon debug. DATE (2009)
Ho Fai Ko, Nicola Nicolici
Resource-Efficient Programmable Trigger Units for Post-Silicon Validation. ETS (2009)
Adam B. Kinsman, Nicola Nicolici
Finite Precision bit-width allocation using SAT-Modulo Theory. DATE (2009)
Ehab Anis Daoud, Nicola Nicolici
Real-Time Lossless Compression for Silicon Debug. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28 (9) (2009)
Nicola Nicolici, Ho Fai Ko
Design-for-debug for post-silicon validation: Can high-level descriptions help? HLDVT (2009)
Ramin Mafi, Shahin Sirouspour, Brian Moody, Behzad Mahdavikhah, Kaveh Elizeh, Adam B. Kinsman, Nicola Nicolici, Mahyar Fotoohi, D. Madill
Hardware-based parallel computing for real-time haptic rendering of deformable objects. IROS (2008)
Dimitris Gizopoulos, Kaushik Roy, Patrick Girard, Nicola Nicolici, Xiaoqing Wen
Power-Aware Testing and Test Strategies for Low Power Devices. DATE (2008)
Ho Fai Ko, Nicola Nicolici
On Automated Trigger Event Generation in Post-Silicon Validation. DATE (2008)
Ho Fai Ko, Nicola Nicolici
Automated Trace Signals Identification and State Restoration for Improving Observability in Post-Silicon Validation. DATE (2008)
Ehab Anis Daoud, Nicola Nicolici
On Bypassing Blocking Bugs during Post-Silicon Validation. ETS (2008)
Ho Fai Ko, Nicola Nicolici
Automated Scan Chain Division for Reducing Shift and Capture Power During Broadside At-Speed Test. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (11) (2008)
Ho Fai Ko, Adam B. Kinsman, Nicola Nicolici
Distributed Embedded Logic Analysis for Post-Silicon Validation of SOCs. ITC (2008)
Ho Fai Ko, Nicola Nicolici
A Novel Automated Scan Chain Division Method for Shift and Capture Power Reduction in Broadside At-Speed Test. ISQED (2008)
Ho Fai Ko, Nicola Nicolici
Scan Division Algorithm for Shift and Capture Power Reduction for At-Speed Test Using Skewed-Load Test Application Strategy. J. Electron. Test. 24 (4) (2008)
Adam B. Kinsman, Nicola Nicolici
Embedded Deterministic Test Exploiting Care Bit Clustering and Seed Borrowing. ISQED (2008)
Nicola Nicolici, Patrick Girard
Guest Editorial. J. Electron. Test. 24 (4) (2008)
Nicola Nicolici, Xiaoqing Wen
Embedded Tutorial on Low Power Test. ETS (2007)
Qiang Xu, Nicola Nicolici, Krishnendu Chakrabarty
Test Wrapper Design and Optimization Under Power Constraints for Embedded Cores With Multiple Clock Domains. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (8) (2007)
Erik Jan Marinissen, Axel Jantsch, Nicola Nicolici
DATE 07 workshop on diagnostic services in NoCs. IEEE Des. Test Comput. 24 (5) (2007)
Ehab Anis, Nicola Nicolici
Interactive presentation: Low cost debug architecture using lossy compression for silicon debug. DATE (2007)
Ehab Anis, Nicola Nicolici
On using lossless compression of debug data in embedded logic analysis. ITC (2007)
Erik Jan Marinissen, Nicola Nicolici
Editorial Silicon Debug and Diagnosis. IET Comput. Digit. Tech. 1 (6) (2007)
Qiang Xu, Nicola Nicolici
Multifrequency TAM design for hierarchical SOCs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (1) (2006)
Ho Fai Ko, Nicola Nicolici
RTL Scan Design for Skewed-Load At-speed Test under Power Constraints. ICCD (2006)
Adam B. Kinsman, Scott Ollivierre, Nicola Nicolici
Diagnosis of Logic Circuits Using Compressed Deterministic Data and On-Chip Response Comparison. IEEE Trans. Very Large Scale Integr. Syst. 14 (5) (2006)
Qiang Xu, Nicola Nicolici
DFT Infrastructure for Broadside Two-Pattern Test of Core-Based SOCs. IEEE Trans. Computers 55 (4) (2006)
Qiang Xu, Nicola Nicolici
Wrapper design for multifrequency IP cores. IEEE Trans. Very Large Scale Integr. Syst. 13 (6) (2005)
Adam B. Kinsman, Nicola Nicolici
Time-multiplexed test data decompression architecture for core-based SOCs with improved utilization of tester channels. ETS (2005)
Qiang Xu, Nicola Nicolici
Modular and rapid testing of SOCs with unwrapped logic blocks. IEEE Trans. Very Large Scale Integr. Syst. 13 (11) (2005)
Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola Nicolici
Synchronization overhead in SOC compressed test. IEEE Trans. Very Large Scale Integr. Syst. 13 (1) (2005)
Qiang Xu, Nicola Nicolici, Krishnendu Chakrabarty
Multi-frequency wrapper design and optimization for embedded cores under average power constraints. DAC (2005)
Ho Fai Ko, Qiang Xu, Nicola Nicolici
Register-transfer level functional scan for hierarchical designs. ASP-DAC (2005)
Qiang Xu, Nicola Nicolici
Modular SOC testing with reduced wrapper count. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24 (12) (2005)
Qiang Xu, Nicola Nicolici
On concurrent test of wrapped cores and unwrapped logic blocks in SOCs. ITC (2005)
Ho Fai Ko, Nicola Nicolici
Functional Illinois Scan Design at RTL. ICCD (2004)
Nicola Nicolici, Bashir M. Al-Hashimi
Testability Trade-Offs for BIST Data Paths. J. Electron. Test. 20 (2) (2004)
Qiang Xu, Nicola Nicolici
Wrapper Design for Testing IP Cores with Multiple Clock Domains. DATE (2004)

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Publication Activity (10 Years)

Top Topics

Top Venues

Nicola Nicolici