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On Using On-Chip Clock Tuning Elements to Address Delay Degradation Due to Circuit Aging.
Zahra Lak
Nicola Nicolici
Published in:
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2012)
Keyphrases
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high speed
power dissipation
power consumption
analog vlsi
circuit design
phase locked loop
low power
duty cycle
chip design
cmos technology
physical design
logic circuits
clock frequency
evolvable hardware
real time
low cost
neural network
nm technology
steady state