Ho Fai Ko

Publication Activity (10 Years)

Years Active: 2004-2013
Publications (10 Years): 0

Top Topics

Programmable Logic

Evolutionary Algorithm

Generation Process

Top Venues

IEEE Trans. Computers

Publications

Adam B. Kinsman, Ho Fai Ko, Nicola Nicolici
Hardware-efficient on-chip generation of time-extensive constrained-random sequences for in-system validation. DAC (2013)
Adam B. Kinsman, Ho Fai Ko, Nicola Nicolici
In-system constrained-random stimuli generation for post-silicon validation. ITC (2012)
Ho Fai Ko, Nicola Nicolici
Mapping Trigger Conditions onto Trigger Units during Post-silicon Validation and Debugging. IEEE Trans. Computers 61 (11) (2012)
Ho Fai Ko, Adam B. Kinsman, Nicola Nicolici
Design-for-Debug Architecture for Distributed Embedded Logic Analysis. IEEE Trans. Very Large Scale Integr. Syst. 19 (8) (2011)
Ho Fai Ko, Nicola Nicolici
Combining scan and trace buffers for enhancing real-time observability in post-silicon debugging. ETS (2010)
Ho Fai Ko, Nicola Nicolici
Automated trace signals selection using the RTL descriptions. ITC (2010)
Ho Fai Ko, Nicola Nicolici
Algorithms for State Restoration and Trace-Signal Selection for Data Acquisition in Silicon Debug. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28 (2) (2009)
Ho Fai Ko, Nicola Nicolici
Resource-Efficient Programmable Trigger Units for Post-Silicon Validation. ETS (2009)
Nicola Nicolici, Ho Fai Ko
Design-for-debug for post-silicon validation: Can high-level descriptions help? HLDVT (2009)
Ho Fai Ko, Nicola Nicolici
On Automated Trigger Event Generation in Post-Silicon Validation. DATE (2008)
Ho Fai Ko, Nicola Nicolici
Automated Trace Signals Identification and State Restoration for Improving Observability in Post-Silicon Validation. DATE (2008)
Ho Fai Ko, Nicola Nicolici
Automated Scan Chain Division for Reducing Shift and Capture Power During Broadside At-Speed Test. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (11) (2008)
Ho Fai Ko, Adam B. Kinsman, Nicola Nicolici
Distributed Embedded Logic Analysis for Post-Silicon Validation of SOCs. ITC (2008)
Ho Fai Ko, Nicola Nicolici
A Novel Automated Scan Chain Division Method for Shift and Capture Power Reduction in Broadside At-Speed Test. ISQED (2008)
Ho Fai Ko, Nicola Nicolici
Scan Division Algorithm for Shift and Capture Power Reduction for At-Speed Test Using Skewed-Load Test Application Strategy. J. Electron. Test. 24 (4) (2008)
Ho Fai Ko, Nicola Nicolici
RTL Scan Design for Skewed-Load At-speed Test under Power Constraints. ICCD (2006)
Ho Fai Ko, Qiang Xu, Nicola Nicolici
Register-transfer level functional scan for hierarchical designs. ASP-DAC (2005)
Ho Fai Ko, Nicola Nicolici
Functional Illinois Scan Design at RTL. ICCD (2004)
Ho Fai Ko, Nicola Nicolici
Functional Scan Chain Design at RTL for Skewed-Load Delay Fault Testing. Asian Test Symposium (2004)