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FPGA Power Reduction by Guarded Evaluation Considering Logic Architecture.
Chirag Ravishankar
Jason Helge Anderson
Andrew A. Kennings
Published in:
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2012)
Keyphrases
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power reduction
power consumption
low power
multithreading
hardware architecture
pipelined architecture
real time
power saving
hardware design
hardware implementation
high speed
hidden markov models
image processing
parallel processing
data management
power dissipation
pattern recognition