Leakage power reduction in FPGA DSP circuits through algorithmic noise tolerance.
Edgar Mora-SanchezJason Helge AndersonPublished in: ReConFig (2013)
Keyphrases
- power reduction
- noise tolerance
- digital signal processing
- low power
- power consumption
- power dissipation
- noise tolerant
- high speed
- power saving
- low cost
- signal processing
- verilog hdl
- corner detectors
- candidate pruning
- data flow
- multi threaded
- linear threshold
- multi class
- pattern recognition
- neural network
- energy efficiency
- noisy data
- soft margin
- response time
- pairwise
- feature space