Synthesizable-from-C Embedded Processor Based on MIPS-ISA and OISC.

Tanvir Ahmed Noriaki Sakamoto Jason Helge Anderson Yuko Hara-Azumi

Published in: EUC (2015)

Keyphrases

high speed
embedded processors
dynamic random access memory
high end
single chip
parallel processing
computer systems
embedded systems
distributed memory
error detection
multi core processors
instruction set
instruction set architecture