Sensei: An area-reduction advisor for FPGA high-level synthesis.
Hsuan HsiaoJason Helge AndersonPublished in: DATE (2018)
Keyphrases
- high level synthesis
- parallel architecture
- hardware implementation
- real time image processing
- field programmable gate array
- high speed
- parallel processing
- power reduction
- verilog hdl
- hardware design
- low cost
- single chip
- efficient implementation
- signal processing
- design space exploration
- wireless sensor networks
- pairwise