A technique for minimizing power during FPGA placement.

Kristofer Vorwerk Madhu Raman Julien Dunoyer Yaun-Chung Hsu Arun Kundu Andrew A. Kennings

Published in: FPL (2008)

Keyphrases

high speed
power consumption
real time
hardware implementation
real time image processing
power reduction
information retrieval
neural network
pattern recognition
low cost
signal processing