Guilherme Flach

Publication Activity (10 Years)

Years Active: 2006-2017
Publications (10 Years): 6

Top Topics

Miller Tucker Zemlin

Visualization Tools

Top Venues

Publications

Guilherme Flach, Mateus Fogaça, Jucemar Monteiro, Marcelo O. Johann, Ricardo Augusto da Luz Reis
Rsyn: An Extensible Physical Synthesis Framework. ISPD (2017)
Mateus Fogaça, Guilherme Flach, Marcelo O. Johann, Ricardo Augusto da Luz Reis
Improving placement algorithms by using visualization tools. NEWCAS (2016)
Jorge L. Tonfat, Guilherme Flach, Ricardo Reis
Leakage current analysis in static CMOS logic gates for a transistor network design approach. PATMOS (2016)
Mateus Fogaça, Guilherme Flach, Jucemar Monteiro, Marcelo O. Johann, Ricardo Reis
Quadratic timing objectives for incremental timing-driven placement optimization. ICECS (2016)
Guilherme Flach, Mateus Fogaça, Jucemar Monteiro, Marcelo O. Johann, Ricardo Augusto da Luz Reis
Drive Strength Aware Cell Movement Techniques for Timing Driven Placement. ISPD (2016)
Jucemar Monteiro, Nima Karimpour Darav, Guilherme Flach, Mateus Fogaça, Ricardo Augusto da Luz Reis, Andrew A. Kennings, Marcelo O. Johann, Laleh Behjat
Routing-Aware Incremental Timing-Driven Placement. ISVLSI (2016)
Jucemar Monteiro, Guilherme Flach, Marcelo O. Johann, José Luís Almada Güntzel
An analytical timing-driven algorithm for detailed placement. LASCAS (2015)
Julia Casarin Puget, Guilherme Flach, Marcelo O. Johann, Ricardo Augusto da Luz Reis
Jezz: An Effective Legalization Algorithm for Minimum Displacement. SBCCI (2015)
Guilherme Flach, Jucemar Monteiro, Mateus Fogaça, Julia Casarin Puget, Paulo F. Butzen, Marcelo O. Johann, Ricardo Augusto da Luz Reis
An Incremental Timing-Driven flow using quadratic formulation for detailed placement. VLSI-SoC (2015)
Guilherme Flach, Tiago Reimann, Gracieli Posser, Marcelo O. Johann, Ricardo Reis
Effective Method for Simultaneous Gate Sizing and $V$ th Assignment Using Lagrangian Relaxation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33 (4) (2014)
Tania Mara Ferla, Guilherme Flach, Ricardo Reis
A tool to simulate optical lithography in nanoCMOs. I2MTC (2014)
Guilherme Flach, Tiago Reimann, Gracieli Posser, Marcelo O. Johann, Ricardo Reis
Simultaneous gate sizing and Vth assignment using Lagrangian Relaxation and delay sensitivities. ISVLSI (2013)
Tiago Reimann, Gracieli Posser, Guilherme Flach, Marcelo O. Johann, Ricardo Reis
Simultaneous gate sizing and Vt assignment using Fanin/Fanout ratio and Simulated Annealing. ISCAS (2013)
Matthew R. Guthaus, Xuchu Hu, Gustavo Wilke, Guilherme Flach, Ricardo Reis
High-performance clock mesh optimization. ACM Trans. Design Autom. Electr. Syst. 17 (3) (2012)
Gracieli Posser, Guilherme Flach, Gustavo Wilke, Ricardo Reis
Transistor sizing and gate sizing using geometric programming considering delay minimization. NEWCAS (2012)
Guilherme Flach, Marcelo O. Johann, Ricardo Reis
Quadratic placement with single-iteration linear system solver. SBCCI (2011)
Gracieli Posser, Guilherme Flach, Gustavo Wilke, Ricardo Reis
Gate Sizing Minimizing Delay and Area. ISVLSI (2011)
Guilherme Flach, Gustavo Wilke, Marcelo O. Johann, Ricardo Reis
A Mesh-Buffer Displacement Optimization Strategy. ISVLSI (2010)
Guilherme Flach, Marcelo O. Johann, Renato Fernandes Hentschke, Ricardo Reis
Cell placement on graphics processing units. SBCCI (2007)
Renato Fernandes Hentschke, Guilherme Flach, Felipe Pinto, Ricardo Reis
3D-Vias Aware Quadratic Placement for 3D VLSI Circuits. ISVLSI (2007)
Renato Fernandes Hentschke, Guilherme Flach, Felipe Pinto, Ricardo Reis
Quadratic placement for 3d circuits using z-cell shifting, 3d iterative refinement and simulated annealing. SBCCI (2006)