Renato Fernandes Hentschke

Publication Activity (10 Years)

Years Active: 2002-2019
Publications (10 Years): 1

Top Topics

Declarative Language

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

Gyuszi Suto, Geoff S. Greenleaf, Phanindra Bhagavatula, Heinrich R. Fischer, Sanjay K. Soni, Brian H. Miller, Renato Fernandes Hentschke
Declarative Language for Geometric Pattern Matching in VLSI Process Rule Modeling. ISPD (2019)
Muhammet Mustafa Ozdal, Renato Fernandes Hentschke
Algorithms for Maze Routing With Exact Matching Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33 (1) (2014)
Muhammet Mustafa Ozdal, Renato Fernandes Hentschke
Maze routing algorithms with exact matching constraints for analog and mixed signal designs. ICCAD (2012)
Renato Fernandes Hentschke, Marcelo O. Johann, Ricardo Reis
Posicionamento de Circuitos 3D Considerando o Planejamento de 3D-Vias. RITA 19 (1) (2012)
Muhammet Mustafa Ozdal, Renato Fernandes Hentschke
An Algorithmic Study of Exact Route Matching for Integrated Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30 (12) (2011)
Muhammet Mustafa Ozdal, Renato Fernandes Hentschke
Exact route matching algorithms for analog and mixed signal integrated circuits. ICCAD (2009)
Renato Fernandes Hentschke, Jagannathan Narasimhan, Marcelo O. Johann, Ricardo Reis
Maze Routing Steiner Trees With Delay Versus Wire Length Tradeoff. IEEE Trans. Very Large Scale Integr. Syst. 17 (8) (2009)
Renato Fernandes Hentschke, Ricardo Reis
A 3D-Via Legalization Algorithm for 3D VLSI Circuits and its Impact on Wire Length. ISCAS (2007)
Renato Fernandes Hentschke, Jaganathan Narasimham, Marcelo O. Johann, Ricardo Augusto da Luz Reis
Maze routing steiner trees with effective critical sink optimization. ISPD (2007)
Guilherme Flach, Marcelo O. Johann, Renato Fernandes Hentschke, Ricardo Reis
Cell placement on graphics processing units. SBCCI (2007)
Renato Fernandes Hentschke, Guilherme Flach, Felipe Pinto, Ricardo Reis
3D-Vias Aware Quadratic Placement for 3D VLSI Circuits. ISVLSI (2007)
Renato Fernandes Hentschke, Guilherme Flach, Felipe Pinto, Ricardo Reis
Quadratic placement for 3d circuits using z-cell shifting, 3d iterative refinement and simulated annealing. SBCCI (2006)
Renato Fernandes Hentschke, Sandro Sawicki, Marcelo O. Johann, Ricardo Augusto da Luz Reis
An Algorithm for I/O Partitioning Targeting 3D Circuits and Its Impact on 3D-Vias. VLSI-SoC (2006)
Sandro Sawicki, Renato Fernandes Hentschke, Marcelo O. Johann, Ricardo Reis
Unbalacing the I/O Pins Partitioning for Minimizing Inter-Tier Vias in 3D VLSI Circuits. ICECS (2006)
Renato Fernandes Hentschke, Sandro Sawicki, Marcelo O. Johann, Ricardo Reis
A Method for I/O Pins Partitioning Targeting 3D VLSI Circuits. VLSI-SoC (Selected Papers) (2006)
Renato Fernandes Hentschke, Marcelo O. Johann, Ricardo Reis
Blue Macaw: A Didactic Placement Tool Using Simulated Annealing. EDUTECH (2005)
Renato Fernandes Hentschke, Jagannathan Narasimhan, David S. Kung
Improving run times by pruned application of synthesis transforms. SBCCI (2005)
Fernanda Lima Kastensmidt, Gustavo Neuberger, Renato Fernandes Hentschke, Luigi Carro, Ricardo Reis
Designing Fault-Tolerant Techniques for SRAM-Based FPGAs. IEEE Des. Test Comput. 21 (6) (2004)
Júlio C. B. de Mattos, Lisane B. de Brisolara, Renato Fernandes Hentschke, Luigi Carro, Flávio Rech Wagner
Design Space Exploration with Automatic Generation of IP-Based Embedded Software. DIPES (2004)
Renato Fernandes Hentschke, Ricardo Reis
Plic-Plac: a novel constructive algorithm for placement. ISCAS (5) (2003)
Renato Fernandes Hentschke, Marcelo de Oliveira Johann, Ricardo Augusto da Luz Reis
A study on the performance of fast initial placement algorithms. VLSI-SOC (2003)
Renato Fernandes Hentschke, Ricardo Augusto da Luz Reis
Improving Simulated Annealing Placement by Applying Random and Greedy Mixed Perturbations. SBCCI (2003)
Renato Fernandes Hentschke, Felipe S. Marques, Fernanda Lima, Luigi Carro, Altamiro Amadeu Susin, Ricardo Reis
Analyzing Area and Performance Penalty of Protecting Different Digital Modules with Hamming Code and Triple Modular Redundancy. SBCCI (2002)