Steven M. Burns

Publication Activity (10 Years)

Years Active: 1989-2023
Publications (10 Years): 19

Top Topics

Learning From Experience

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Analog Circuits

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

Kishor Kunal, Tonmoy Dhar, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Jiang Hu, Ramesh Harjani, Sachin S. Sapatnekar
GNN-Based Hierarchical Annotation for Analog Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (9) (2023)
Ramprasath Srinivasa Gopalakrishnan, Meghna Madhusudan, Arvind K. Sharma, Jitesh Poojary, Soner Yaldiz, Ramesh Harjani, Steven M. Burns, Sachin S. Sapatnekar
A Generalized Methodology for Well Island Generation and Well-tap Insertion in Analog/Mixed-signal Layouts. ACM Trans. Design Autom. Electr. Syst. 28 (5) (2023)
Susmita Dey Manasi, Suvadeep Banerjee, Abhijit Davare, Anton A. Sorokin, Steven M. Burns, Desmond A. Kirkpatrick, Sachin S. Sapatnekar
Reusing GEMM Hardware for Efficient Execution of Depthwise Separable Convolution on ASIC-Based DNN Accelerators. ASP-DAC (2023)
Tonmoy Dhar, Ramprasath S, Jitesh Poojary, Soner Yaldiz, Steven M. Burns, Ramesh Harjani, Sachin S. Sapatnekar
A Charge Flow Formulation for Guiding Analog/Mixed-Signal Placement. DATE (2022)
Ramprasath S, Meghna Madhusudan, Arvind K. Sharma, Jitesh Poojary, Soner Yaldiz, Ramesh Harjani, Steven M. Burns, Sachin S. Sapatnekar
Analog/Mixed-Signal Layout Optimization using Optimal Well Taps. ISPD (2022)
Tonmoy Dhar, Kishor Kunal, Yaguang Li, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Ramesh Harjani, Jiang Hu, Desmond A. Kirkpatrick, Parijat Mukherjee, Soner Yaldiz, Sachin S. Sapatnekar
ALIGN: A System for Automating Analog Layout. IEEE Des. Test 38 (2) (2021)
Arvind K. Sharma, Meghna Madhusudan, Steven M. Burns, Soner Yaldiz, Parijat Mukherjee, Ramesh Harjani, Sachin S. Sapatnekar
Performance-Aware Common-Centroid Placement and Routing of Transistor Arrays in Analog Circuits. ICCAD (2021)
Tonmoy Dhar, Kishor Kunal, Yaguang Li, Yishuang Lin, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Steven M. Burns, Ramesh Harjani, Jiang Hu, Parijat Mukherjee, Soner Yaldiz, Sachin S. Sapatnekar
Machine Learning Techniques in Analog Layout Automation. ISPD (2021)
Arvind K. Sharma, Meghna Madhusudan, Steven M. Burns, Parijat Mukherjee, Soner Yaldiz, Ramesh Harjani, Sachin S. Sapatnekar
Common-Centroid Layouts for Analog Circuits: Advantages and Limitations. DATE (2021)
Tonmoy Dhar, Kishor Kunal, Yaguang Li, Yishuang Lin, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Steven M. Burns, Ramesh Harjani, Jiang Hu, Parijat Mukherjee, Soner Yaldiz, Sachin S. Sapatnekar
The ALIGN Open-Source Analog Layout Generator: v1.0 and Beyond (Invited talk). ICCAD (2020)
Kishor Kunal, Tonmoy Dhar, Yaguang Li, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Ramesh Harjani, Jiang Hu, Parijat Mukherjee, Sachin S. Sapatnekar
Learning from Experience: Applying ML to Analog Circuit Design. ISPD (2020)
Kishor Kunal, Tonmoy Dhar, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Jiang Hu, Ramesh Harjani, Sachin S. Sapatnekar
GANA: Graph Convolutional Network Based Automated Netlist Annotation for Analog Circuits. DATE (2020)
Tonmoy Dhar, Kishor Kunal, Yaguang Li, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Ramesh Harjani, Jiang Hu, Desmond A. Kirkpatrick, Parijat Mukherjee, Sachin S. Sapatnekar, Soner Yaldiz
ALIGN: A System for Automating Analog Layout. CoRR (2020)
Nikolay Ryzhenko, Steven M. Burns, Anton Sorokin, Mikhail Talalay
Pin Access-Driven Design Rule Clean and DFM Optimized Routing of Standard Cells under Boolean Constraints. ISPD (2019)
Kishor Kunal, Meghna Madhusudan, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Ramesh Harjani, Jiang Hu, Desmond A. Kirkpatrick, Sachin S. Sapatnekar
ALIGN: Open-Source Analog Layout Automation from the Ground Up. DAC (2019)
Andrey Ayupov, Serif Yesil, Muhammet Mustafa Ozdal, Taemin Kim, Steven M. Burns, Ozcan Ozturk
A Template-Based Design Methodology for Graph-Parallel Hardware Accelerators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (2) (2018)
Michael Barrow, Steven M. Burns, Ryan Kastner
A FPGA Accelerator for Real-Time 3D Non-rigid Registration Using Tree Reweighted Message Passing and Dynamic Markov Random Field Generation. FPL (2018)
Muhammet Mustafa Ozdal, Serif Yesil, Taemin Kim, Andrey Ayupov, John Greth, Steven M. Burns, Ozcan Ozturk
Graph Analytics Accelerators for Cognitive Systems. IEEE Micro 37 (1) (2017)
Muhammet Mustafa Ozdal, Serif Yesil, Taemin Kim, Andrey Ayupov, John Greth, Steven M. Burns, Özcan Özturk
Energy Efficient Architecture for Graph Analytics Accelerators. ISCA (2016)
Serif Yesil, Muhammet Mustafa Ozdal, Taemin Kim, Andrey Ayupov, Steven M. Burns, Ozcan Ozturk
Hardware Accelerator Design for Data Centers. ICCAD (2015)
Muhammet Mustafa Ozdal, Aamer Jaleel, Paolo Narváez, Steven M. Burns, Ganapati Srinivasa
Wavelet-Based Trace Alignment Algorithms for Heterogeneous Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34 (3) (2015)
Muhammet Mustafa Ozdal, Serif Yesil, Taemin Kim, Andrey Ayupov, Steven M. Burns, Ozcan Ozturk
Architectural Requirements for Energy Efficient Execution of Graph Analytics Applications. ICCAD (2015)
Muhammet Mustafa Ozdal, Aamer Jaleel, Paolo Narváez, Steven M. Burns, Ganapati Srinivasa
Trace alignment algorithms for offline workload analysis of heterogeneous architectures. ICCAD (2013)
Muhammet Mustafa Ozdal, Chirayu Amin, Andrey Ayupov, Steven M. Burns, Gustavo R. Wilke, Cheng Zhuo
An improved benchmark suite for the ISPD-2013 discrete cell sizing contest. ISPD (2013)
Muhammet Mustafa Ozdal, Chirayu Amin, Andrey Ayupov, Steven M. Burns, Gustavo R. Wilke, Cheng Zhuo
The ISPD-2012 discrete cell sizing contest and benchmark suite. ISPD (2012)
Muhammet Mustafa Ozdal, Steven M. Burns, Jiang Hu
Algorithms for Gate Sizing and Device Parameter Selection for High-Performance Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31 (10) (2012)
Nikolai Ryzhenko, Steven M. Burns
Standard cell routing via boolean satisfiability. DAC (2012)
Muhammet Mustafa Ozdal, Steven M. Burns, Jiang Hu
Gate sizing and device technology selection algorithms for high-performance industrial designs. ICCAD (2011)
Andrey Ayupov, Steven M. Burns
A trace compression algorithm targeting power estimation of long benchmarks. ICCAD (2011)
Nikolai Ryzhenko, Steven M. Burns
Physical synthesis onto a layout fabric with regular diffusion and polysilicon geometries. DAC (2011)
Steven M. Burns, Mahesh Ketkar, Noel Menezes, Keith A. Bowman, James W. Tschanz, Vivek De
Comparative Analysis of Conventional and Statistical Design Techniques. DAC (2007)
Tanay Karnik, Yibin Ye, James W. Tschanz, Liqiong Wei, Steven M. Burns, Venkatesh Govindarajulu, Vivek De, Shekhar Borkar
Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors. DAC (2002)
Jordi Cortadella, Michael Kishinevsky, Steven M. Burns, Alex Kondratyev, Luciano Lavagno, Ken S. Stevens, Alexander Taubin, Alexandre Yakovlev
Lazy transition systems and asynchronous circuit synthesis withrelative timing assumptions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21 (2) (2002)
Jordi Cortadella, Michael Kishinevsky, Steven M. Burns, Ken S. Stevens
Synthesis of asynchronous control circuits with automatically generated relative timing assumptions. ICCAD (1999)
Ken S. Stevens, Shai Rotem, Steven M. Burns, Jordi Cortadella, Ran Ginosar, Michael Kishinevsky, Marly Roncken
CAD Directions for High Performance Asynchronous Circuits. DAC (1999)
Henrik Hulgaard, Steven M. Burns
Bounded Delay Timing Analysis of a Class of CSP Programs. Formal Methods Syst. Des. 11 (3) (1997)
Steven M. Burns
General conditions for the decomposition of state holding elements. ASYNC (1996)
Carl Ebeling, Larry McMurchie, Scott Hauck, Steven M. Burns
Placement and routing tools for the Triptych FPGA. IEEE Trans. Very Large Scale Integr. Syst. 3 (4) (1995)
Henrik Hulgaard, Steven M. Burns, Gaetano Borriello
Testing asynchronous circuits: A survey. Integr. 19 (3) (1995)
Henrik Hulgaard, Steven M. Burns, Tod Amon, Gaetano Borriello
An Algorithm for Exact Bounds on the Time Separation of Events in Concurrent Systems. IEEE Trans. Computers 44 (11) (1995)
Henrik Hulgaard, Steven M. Burns
Efficient Timing Analysis of a Class of Petri Nets. CAV (1995)
Gaetano Borriello, Carl Ebeling, Scott Hauck, Steven M. Burns
The Triptych FPGA architecture. IEEE Trans. Very Large Scale Integr. Syst. 3 (4) (1995)
Henrik Hulgaard, Steven M. Burns
Bounded delay timing analysis of a class of CSP programs with choice. ASYNC (1994)
Scott Hauck, Steven M. Burns, Gaetano Borriello, Carl Ebeling
An FPGA for Implementing Asynchronous Circuits. IEEE Des. Test Comput. 11 (3) (1994)
Henrik Hulgaard, Steven M. Burns, Tod Amon, Gaetano Borriello
Practical applications of an efficient time separation of events algorithm. ICCAD (1993)
Tod Amon, Henrik Hulgaard, Steven M. Burns, Gaetano Borriello
An Algorithm for Exact Bounds on the Time Separation of Events in Concurrent Systems. ICCD (1993)
Scott Hauck, Gaetano Borriello, Steven M. Burns, Carl Ebeling
MONTAGNE: An FPL for Synchronous and Asynchronous Circuits. FPL (1992)
Alain J. Martin, Steven M. Burns, Tak-Kwan Lee, Drazen Borkovic, Pieter J. Hazewindus
The design of an asynchronous microprocessor. SIGARCH Comput. Archit. News 17 (4) (1989)
Alain J. Martin, Steven M. Burns, Tak-Kwan Lee, Drazen Borkovic, Pieter J. Hazewindus
The first asynchronous microprocessor: the test results. SIGARCH Comput. Archit. News 17 (4) (1989)