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Synthesis of asynchronous control circuits with automatically generated relative timing assumptions.
Jordi Cortadella
Michael Kishinevsky
Steven M. Burns
Ken S. Stevens
Published in:
ICCAD (1999)
Keyphrases
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knowledge base
automatically generated
automatically generate
asynchronous circuits
high level synthesis
delay insensitive
manually generated
automatically generating
manually constructed
manually created
automatically created
logic synthesis
control system
information retrieval
high speed
analog circuits