Carl Ebeling

Publication Activity (10 Years)

Years Active: 1984-2020
Publications (10 Years): 2

Top Topics

Graphics Hardware

Reference Genome

Dynamic Reconfiguration

Top Venues

Publications

Jesmin Jahan Tithi, Fabrizio Petrini, Hongbo Rong, Andrei Valentin, Carl Ebeling
Mapping Stencils on Coarse-grained Reconfigurable Spatial Architecture. CoRR (2020)
Carl Ebeling, Dana How, David M. Lewis, Herman Schmit
Stratix™ 10 High Performance Routable Clock Networks. FPGA (2016)
Robin Panda, Carl Ebeling, Scott Hauck
Adding dataflow-driven execution control to a Coarse-Grained Reconfigurable Array. FPL (2012)
Corey B. Olson, Maria Kim, Cooper Clauson, Boris Kogon, Carl Ebeling, Scott Hauck, Walter L. Ruzzo
Hardware Acceleration of Short Read Mapping. FCCM (2012)
Jacob Nelson, Brandon Myers, A. H. Hunter, Preston Briggs, Luis Ceze, Carl Ebeling, Dan Grossman, Simon Kahan, Mark Oskin
Crunching Large Graphs with Commodity Processors. HotPar (2011)
Brian Van Essen, Robin Panda, Aaron Wood, Carl Ebeling, Scott Hauck
Energy-efficient specialization of functional units in a coarse-grained reconfigurable array. FPGA (2011)
Brian Van Essen, Robin Panda, Aaron Wood, Carl Ebeling, Scott Hauck
Managing Short-Lived and Long-Lived Values in Coarse-Grained Reconfigurable Arrays. FPL (2010)
Brian Van Essen, Aaron Wood, Allan Carroll, Stephen Friedman, Robin Panda, Benjamin Ylvisaker, Carl Ebeling, Scott Hauck
Static versus scheduled interconnect in Coarse-Grained Reconfigurable Arrays. FPL (2009)
Stephen Friedman, Allan Carroll, Brian Van Essen, Benjamin Ylvisaker, Carl Ebeling, Scott Hauck
SPR: an architecture-adaptive CGRA mapping tool. FPGA (2009)
Carl Ebeling, Brian French
Abstract Verilog: A Hardware Description Language for Novice Students. MSE (2007)
Benjamin Ylvisaker, Brian Van Essen, Carl Ebeling
A type architecture for hybrid micro-parallel computers. FPGA (2006)
Benjamin Ylvisaker, Brian Van Essen, Carl Ebeling
A Type Architecture for Hybrid Micro-Parallel Computers. FCCM (2006)
Carl Ebeling
Configurable Computing Platforms - Promises, Promises. ASAP (2006)
Allan Carroll, Carl Ebeling
Reducing the Space Complexity of Pipelined Routing Using Modified Range Encoding. FPL (2006)
Akshay Sharma, Carl Ebeling, Scott Hauck
PipeRoute: a pipelining-aware router for reconfigurable architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (3) (2006)
Akshay Sharma, Carl Ebeling, Scott Hauck
Architecture Adaptive Routability-Driven Placement for FPGAs (abstract only). FPGA (2005)
Akshay Sharma, Carl Ebeling, Scott Hauck
Architecture-Adaptive Routability-Driven Placement for FPGAs. FPL (2005)
Song Li, Carl Ebeling
QuickRoute: a fast routing algorithm for pipelined architectures. FPT (2004)
Carl Ebeling, Chris Fisher, Guanbin Xing, Manyuan Shen, Hui Liu
Implementing an OFDM Receiver on the RaPiD Reconfigurable Architecture. IEEE Trans. Computers 53 (11) (2004)
Akshay Sharma, Katherine Compton, Carl Ebeling, Scott Hauck
Exploration of pipelined FPGA interconnect structures. FPGA (2004)
John F. Keane, Christopher Bradley, Carl Ebeling
A compiled accelerator for biological cell signaling simulations. FPGA (2004)
Carl Ebeling, Chris Fisher, Guanbin Xing, Manyuan Shen, Hui Liu
Implementing an OFDM Receiver on the RaPiD Reconfigurable Architecture. FPL (2003)
Akshay Sharma, Carl Ebeling, Scott Hauck
PipeRoute: a pipelining-aware router for FPGAs. FPGA (2003)
Chris Fisher, Kevin Rennie, Guanbin Xing, Stefan G. Berg, Kevin Bolding, John H. Naegle, Daniel Parshall, Dmitriy Portnov, Adnan Sulejmanpasic, Carl Ebeling
An Emulator for Exploring RaPiD Configurable Computing Architectures. FPL (2001)
Pak K. Chan, Martine D. F. Schlag, Carl Ebeling, Larry McMurchie
Distributed-memory parallel routing for field-programmable gatearrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19 (8) (2000)
Darren C. Cronquist, Chris Fisher, Miguel E. Figueroa, Paul Franklin, Carl Ebeling
Architecture Design of Reconfigurable Pipelined Datapaths. ARVLSI (1999)
Darren C. Cronquist, Paul Franklin, Stefan G. Berg, Carl Ebeling
Specifying and Compiling Applications for RaPiD. FCCM (1998)
Soha Hassoun, Carl Ebeling
Using precomputation in architecture and logic resynthesis. ICCAD (1998)
Scott Hauck, Gaetano Borriello, Carl Ebeling
Mesh routing topologies for multi-FPGA systems. IEEE Trans. Very Large Scale Integr. Syst. 6 (3) (1998)
Carl Ebeling, Darren C. Cronquist, Paul Franklin, Jason Secosky, Stefan G. Berg
Mapping applications to the RaPiD configurable architecture. FCCM (1997)
Neil R. McKenzie, Kevin Bolding, Carl Ebeling, Lawrence Snyder
ChaosLAN: Design and Implementation of a Gigabit LAN Using Chaotic Routing. PCRCW (1997)
Carl Ebeling
Whither Configurable Computing? HICSS (1) (1997)
Carl Ebeling, Darren C. Cronquist, Paul Franklin
Configurable computing: the catalyst for high-performance architectures. ASAP (1997)
William H. Mangione-Smith, Brad Hutchins, David L. Andrews, André DeHon, Carl Ebeling, Reiner W. Hartenstein, Oskar Mencer, John Morris, Krishna V. Palem, Viktor K. Prasanna, Henk A. E. Spaanenburg
Seeking Solutions in Configurable Computing. Computer 30 (12) (1997)
Carl Ebeling, Darren C. Cronquist, Paul Franklin
RaPiD - Reconfigurable Pipelined Datapath. FPL (1996)
Soha Hassoun, Carl Ebeling
Architectural Retiming: Pipelining Latency-Constrained Circuts. DAC (1996)
Carl Ebeling, Brian Lockyear
On the performance of level-clocked circuits. ARVLSI (1995)
Carl Ebeling, Larry McMurchie, Scott Hauck, Steven M. Burns
Placement and routing tools for the Triptych FPGA. IEEE Trans. Very Large Scale Integr. Syst. 3 (4) (1995)
Larry McMurchie, Carl Ebeling
PathFinder: A Negotiation-based Performance-driven Router for FPGAs. FPGA (1995)
Gaetano Borriello, Carl Ebeling, Scott Hauck, Steven M. Burns
The Triptych FPGA architecture. IEEE Trans. Very Large Scale Integr. Syst. 3 (4) (1995)
Neil R. McKenzie, Kevin Bolding, Carl Ebeling, Lawrence Snyder
CRANIUM: An Interface for Message Passing on Adaptive Packet Routing Networks. PCRCW (1994)
Scott Hauck, Gaetano Borriello, Carl Ebeling
Mesh Routing Topologies for Multi-FPGA Systems. ICCD (1994)
Scott Hauck, Steven M. Burns, Gaetano Borriello, Carl Ebeling
An FPGA for Implementing Asynchronous Circuits. IEEE Des. Test Comput. 11 (3) (1994)
Brian Lockyear, Carl Ebeling
Optimal retiming of level-clocked circuits using symmetric clock schedules. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13 (9) (1994)
Miles Ohlrich, Carl Ebeling, Eka Ginting, Lisa Sather
SubGemini: Identifying SubCircuits using a Fast Subgraph Isomorphism Algorithm. DAC (1993)
Kevin Bolding, Sen-Ching S. Cheung, Sung-Eun Choi, Carl Ebeling, Soha Hassoun, Ton Anh Ngo, Robert Wille
The chaos router chip: design and implementation of an adaptive router. VLSI (1993)
Brian Lockyear, Carl Ebeling
The practical application of retiming to the design of high-performance systems. ICCAD (1993)
Scott Hauck, Gaetano Borriello, Steven M. Burns, Carl Ebeling
MONTAGNE: An FPL for Synchronous and Asynchronous Circuits. FPL (1992)
Hans J. Berliner, Gordon Goetsch, Murray Campbell, Carl Ebeling
Measuring the Performance Potential of Chess Programs. Artif. Intell. 43 (1) (1990)
Tony DeRose, Mary L. Bailey, Bill Barnard, Robert Cypher, David Dobrikin, Carl Ebeling, Smaragda Konstantinidou, Larry McMurchie, Haim Mizrahi, Bill Yost
Apex: two architectures for generating parametric curves and surfaces. Vis. Comput. 5 (5) (1989)
Hans J. Berliner, Carl Ebeling
Pattern Knowledge and Search: The SUPREM Architecture. Artif. Intell. 38 (2) (1989)
Carl Ebeling, Zhanbing Wu
WireLisp: combining graphics and procedures in a circuit specification language. ICCAD (1989)
Carl Ebeling
GeminiII: a second generation layout validation program. ICCAD (1988)
Hans J. Berliner, Carl Ebeling
The SUPREM Architecture: A New Intelligent Paradigm. Artif. Intell. 28 (1) (1986)
Carl Ebeling, Andrew J. Palay
The Design and Implementation of a VLSI Chess Move Generator. ISCA (1984)