Pak K. Chan

Publication Activity (10 Years)

Years Active: 1989-2003
Publications (10 Years): 0

Publications

Pak K. Chan, Martine D. F. Schlag
Parallel placement for field-programmable gate arrays. FPGA (2003)
Pak K. Chan, Martine D. F. Schlag, Carl Ebeling, Larry McMurchie
Distributed-memory parallel routing for field-programmable gatearrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19 (8) (2000)
Pak K. Chan, Martine D. F. Schlag
New parallelization and convergence results for NC: a negotiation-based FPGA router. FPGA (2000)
Pak K. Chan, Liter Siek, Hwee C. Tay, Jing H. Su
A low-offset class-AB CMOS operational amplifier. ISCAS (2000)
Pak K. Chan, Mark J. Boyd, Sezer Gören, K. Klenk, V. Kodavati, R. Kundu, M. Margolese, J. Sun, K. Suzuki, E. Thorne, X. Wang, J. Xu, M. Zhu
Reducing Compilation Time of Zhong's FPGA-Based SAT Solver. FCCM (1999)
Jason Y. Zien, Martine D. F. Schlag, Pak K. Chan
Multilevel spectral hypergraph partitioning with arbitrary vertex sizes. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18 (9) (1999)
Jason Y. Zien, Pak K. Chan, Martine D. F. Schlag
Hybrid spectral/iterative partitioning. ICCAD (1997)
Pak K. Chan, Martine D. F. Schlag
Acceleration of an FPGA router. FCCM (1997)
Jason Y. Zien, Martine D. F. Schlag, Pak K. Chan
Multi-level spectral hypergraph partitioning with arbitrary vertex sizes. ICCAD (1996)
Pak K. Chan, Martine D. F. Schlag, Jason Y. Zien
Spectral-based multiway FPGA partitioning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15 (5) (1996)
Pak K. Chan, Martine D. F. Schlag, Jason Y. Zien
Spectral-Based Multi-Way FPGA Partitioning. FPGA (1995)
Martine D. F. Schlag, Jackson Kong, Pak K. Chan
Routability-driven technology mapping for lookup table-based FPGA's. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13 (1) (1994)
Pak K. Chan, Martine D. F. Schlag, Jason Y. Zien
Spectral K-way ratio-cut partitioning and clustering. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13 (9) (1994)
Pak K. Chan, Martine D. F. Schlag, Jason Y. Zien
-Way Ratio-Cut Partitioning and Clustering. DAC (1993)
Martine D. F. Schlag, Pak K. Chan, Jackson Kong
Empirical evaluation of multilevel logic minimization tools for a lookup-table-based field-programmable gate array technology. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12 (5) (1993)
Pak K. Chan, Martine D. F. Schlag, Jason Y. Zien
On Routability Prediction for Field-Programmable Gate Arrays. DAC (1993)
Martine D. F. Schlag, Jackson Kong, Pak K. Chan
Routability-Driven Techology Mapping for LookUp-Table-Based FPGAs. ICCD (1992)
Pak K. Chan, Martine D. F. Schlag, Clark D. Thomborson, Vojin G. Oklobdzija
Delay Optimization of Carry-Skip Adders and Block Carry-Lookahead Adders Using Multidimensional Dynamic Programming. IEEE Trans. Computers 41 (8) (1992)
Pak K. Chan, Martine D. F. Schlag, Clark D. Thomborson, Vojin G. Oklobdzija
Delay optimization of carry-skip adders and block carry-lookahead adders. IEEE Symposium on Computer Arithmetic (1991)
Pak K. Chan
Comments on 'Asymptotic waveform evaluation for timing analysis'. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10 (8) (1991)
Pak K. Chan
Algorithms for Library-Specific Sizing of Combinational Logic. DAC (1990)
Pak K. Chan, Martine D. F. Schlag
Analysis and Design of CMOS Manchester Adders with Variable Carry-Skip. IEEE Trans. Computers 39 (8) (1990)
Pak K. Chan, Kevin Karplus
Computing signal delay in general RC networks by tree/link partitioning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9 (8) (1990)
Pak K. Chan, Martine D. F. Schlag
Analysis and design of CMOS Manchester adders with variable carry-skip. IEEE Symposium on Computer Arithmetic (1989)
Pak K. Chan, Martine D. F. Schlag
Bounds on signal delay in RC mesh networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8 (6) (1989)
Pak K. Chan, Kevin Karplus
Computing Signal Delay in General RC Networks by Tree/Link Partitioning. DAC (1989)