Martine D. F. Schlag

Publication Activity (10 Years)

Years Active: 1983-2003
Publications (10 Years): 0

Publications

Pak K. Chan, Martine D. F. Schlag
Parallel placement for field-programmable gate arrays. FPGA (2003)
Pak K. Chan, Martine D. F. Schlag, Carl Ebeling, Larry McMurchie
Distributed-memory parallel routing for field-programmable gatearrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19 (8) (2000)
Pak K. Chan, Martine D. F. Schlag
New parallelization and convergence results for NC: a negotiation-based FPGA router. FPGA (2000)
Jason Y. Zien, Martine D. F. Schlag, Pak K. Chan
Multilevel spectral hypergraph partitioning with arbitrary vertex sizes. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18 (9) (1999)
Jason Y. Zien, Pak K. Chan, Martine D. F. Schlag
Hybrid spectral/iterative partitioning. ICCAD (1997)
Pak K. Chan, Martine D. F. Schlag
Acceleration of an FPGA router. FCCM (1997)
Martine D. F. Schlag, F. Joel Ferguson
Detection of Multiple Faults in Two-Dimensional ILAs. IEEE Trans. Computers 45 (6) (1996)
Jason Y. Zien, Martine D. F. Schlag, Pak K. Chan
Multi-level spectral hypergraph partitioning with arbitrary vertex sizes. ICCAD (1996)
Pak K. Chan, Martine D. F. Schlag, Jason Y. Zien
Spectral-based multiway FPGA partitioning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15 (5) (1996)
Pak K. Chan, Martine D. F. Schlag, Jason Y. Zien
Spectral-Based Multi-Way FPGA Partitioning. FPGA (1995)
Martine D. F. Schlag, Jackson Kong, Pak K. Chan
Routability-driven technology mapping for lookup table-based FPGA's. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13 (1) (1994)
Pak K. Chan, Martine D. F. Schlag, Jason Y. Zien
Spectral K-way ratio-cut partitioning and clustering. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13 (9) (1994)
Pak K. Chan, Martine D. F. Schlag, Jason Y. Zien
-Way Ratio-Cut Partitioning and Clustering. DAC (1993)
Martine D. F. Schlag, Pak K. Chan, Jackson Kong
Empirical evaluation of multilevel logic minimization tools for a lookup-table-based field-programmable gate array technology. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12 (5) (1993)
Richard Anderson, Simon Kahan, Martine D. F. Schlag
Single-Layer Cylindrical Compaction. Algorithmica 9 (3) (1993)
Pak K. Chan, Martine D. F. Schlag, Jason Y. Zien
On Routability Prediction for Field-Programmable Gate Arrays. DAC (1993)
Martine D. F. Schlag, Jackson Kong, Pak K. Chan
Routability-Driven Techology Mapping for LookUp-Table-Based FPGAs. ICCD (1992)
Pak K. Chan, Martine D. F. Schlag, Clark D. Thomborson, Vojin G. Oklobdzija
Delay Optimization of Carry-Skip Adders and Block Carry-Lookahead Adders Using Multidimensional Dynamic Programming. IEEE Trans. Computers 41 (8) (1992)
Pak K. Chan, Martine D. F. Schlag, Clark D. Thomborson, Vojin G. Oklobdzija
Delay optimization of carry-skip adders and block carry-lookahead adders. IEEE Symposium on Computer Arithmetic (1991)
Pak K. Chan, Martine D. F. Schlag
Analysis and Design of CMOS Manchester Adders with Variable Carry-Skip. IEEE Trans. Computers 39 (8) (1990)
Richard Anderson, Simon Kahan, Martine D. F. Schlag
) Algorithm for 1-D Tile Compaction. WG (1989)
Pak K. Chan, Martine D. F. Schlag
Analysis and design of CMOS Manchester adders with variable carry-skip. IEEE Symposium on Computer Arithmetic (1989)
Pak K. Chan, Martine D. F. Schlag
Bounds on signal delay in RC mesh networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8 (6) (1989)
Richard Anderson, Simon Kahan, Martine D. F. Schlag
An O(n log n) algorithm for 1-D tile compaction. ICCAD (1989)
Ying-Fung Wu, Peter Widmayer, Martine D. F. Schlag, C. K. Wong
Rectilinear Shortest Paths and Minimum Spanning Trees in the Presence of Rectilinear Obstacles. IEEE Trans. Computers 36 (3) (1987)
Martine D. F. Schlag
The planar topology of functional programs. FPCA (1987)
Peter Widmayer, Ying-Fung Wu, Martine D. F. Schlag, Chak-Kuen Wong
On some union and intersection problems for polygons with fixed orientations. Computing 36 (3) (1986)
Dorab Patel, Martine D. F. Schlag, Milos D. Ercegovac
: An Environment for the Multi-level Specification, Analysis, and Synthesis of Hardware Algorithms. FPCA (1985)
Martine D. F. Schlag, Ellen J. Yoffa, Peter S. Hauge, Chak-Kuen Wong
A Method for Improving Cascode-Switch Macro Wirability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 4 (2) (1985)
Martine D. F. Schlag, Lin S. Woo, Chak-Kuen Wong
Maximizing pin alignment by pin permutations. Integr. 2 (4) (1984)
Martine D. F. Schlag, Yuh-Zen Liao, C. K. Wong
An algorithm for optimal two-dimensional compaction of VLSI layouts. Integr. 1 (2-3) (1983)