Reiner W. Hartenstein

Publication Activity (10 Years)

Years Active: 1970-2013
Publications (10 Years): 0

Top Venues

ASAP

Publications

Reiner W. Hartenstein
The tunnel vision syndrome: Massively delaying progress. ASAP (2013)
Reiner W. Hartenstein
The von Neumann Syndrome and the CS Education Dilemma. ARC (2008)
Reiner W. Hartenstein
The Neumann Syndrome calls for a revolution. HPRCTA (2007)
Reiner W. Hartenstein
RAW keynote 2: new horizons of very high performance computing (VHPC): hurdles and chances. IPDPS (2006)
Mauricio Ayala-Rincón, Carlos H. Llanos, Ricardo P. Jacobi, Reiner W. Hartenstein
Prototyping time- and space-efficient computations of algebraic operations over dynamically reconfigurable systems modeled by rewriting-logic. ACM Trans. Design Autom. Electr. Syst. 11 (2) (2006)
Carlos Morra, M. Sackmann, Sunil Shukla, Jürgen Becker, Reiner W. Hartenstein
From Equation to VHDL: Using Rewriting Logic for Automated Function Generation. FPL (2006)
Reiner W. Hartenstein
Mehr Effizienz durch Configware: auch für Supercomputing. Prax. Inf.verarb. Kommun. 29 (2) (2006)
Peter Wintermayr, Reiner W. Hartenstein, Heinrich Meyr, Steve Leibson
Flexibility and low power: a contradiction in terms? ISLPED (2006)
Reiner W. Hartenstein
From Organic Computing to Reconfigurable Supercomputing. ARCS Workshops (2006)
Reiner W. Hartenstein
The re-definition of low power design for HPC: a paradigm shift. SBCCI (2006)
Carlos Morra, M. Sackmann, Jürgen Becker, Reiner W. Hartenstein
Using Rewriting Logic to Generate Different Implementations of Polynomial Approximations in Coarse-Grained Architectures. ReCoSoC (2006)
Carlos Morra, Jürgen Becker, Mauricio Ayala-Rincón, Reiner W. Hartenstein
FELIX: Using Rewriting-Logic for Generating Functionally Equivalent Implementations. FPL (2005)
Reiner W. Hartenstein
The digital divide of computing. Conf. Computing Frontiers (2004)
Mauricio Ayala-Rincón, Ricardo P. Jacobi, Luis G. A. Carvalho, Carlos H. Llanos, Reiner W. Hartenstein
Modeling and prototyping dynamically reconfigurable systems for efficient computation of dynamic programming methods by rewriting-logic. SBCCI (2004)
Reiner W. Hartenstein
The changing role of computer architecture education within CS curricula: invited presentation. WCAE (2004)
Ricardo P. Jacobi, Mauricio Ayala-Rincón, Luis G. A. Carvalho, Carlos H. Llanos, Reiner W. Hartenstein
Reconfigurable Systems for Sequence Alignment and for General Dynamic Programming. WOB (2004)
Mauricio Ayala-Rincón, Rodrigo Borges Nogueira, Carlos H. Llanos, Ricardo P. Jacobi, Reiner W. Hartenstein
Modeling a Reconfigurable System for Computing the FFT in Place via Rewriting-Logic. SBCCI (2003)
Jürgen Becker, Reiner W. Hartenstein
Configware and morphware going mainstream. J. Syst. Archit. 49 (4-6) (2003)
Mauricio Ayala-Rincón, Ricardo P. Jacobi, Carlos H. Llanos, Reiner W. Hartenstein
Using Rewriting-Logic Notation for Funcional Verification in Data-Stream Based Reconfigurable Computing. FDL (2003)
Reiner W. Hartenstein
Are We Really Ready for the Breakthrough? IPDPS (2003)
Mauricio Ayala-Rincón, Rodrigo Borges Nogueira, Carlos H. Llanos, Ricardo P. Jacobi, Reiner W. Hartenstein
Efficient Computation of Algebraic Operations over Dynamically Reconfigurable Systems Specified by Rewriting-Logic Environments. SCCC (2003)
Michael Herz, Reiner W. Hartenstein, Miguel Miranda, Erik Brockmeyer, Francky Catthoor
Memory addressing organization for stream-based reconfigurable computing. ICECS (2002)
Mauricio Ayala-Rincón, Rinaldi Maya Neto, Ricardo P. Jacobi, Carlos H. Llanos, Reiner W. Hartenstein
Applying ELAN Strategies in Simulating Processors over Simple Architectures. Electron. Notes Theor. Comput. Sci. 70 (6) (2002)
Reiner W. Hartenstein
Trends in reconfigurable logic and reconfigurable computing. ICECS (2002)
Mauricio Ayala-Rincón, Reiner W. Hartenstein, Rinaldi Maya Neto, Ricardo P. Jacobi, Carlos H. Llanos
Architectural Specification, Exploration and Simulation Through Rewriting-Logic. Rev. Colomb. de Computación 3 (2) (2002)
Reiner W. Hartenstein
Disruptive Trends by Data-Stream-Based Computing. FPL (2002)
Reiner W. Hartenstein
Coarse grain reconfigurable architecture (embedded tutorial). ASP-DAC (2001)
Reiner W. Hartenstein
Reconfigurable Computing: A New Business Model and its Impact on SoC Design. DSD (2001)
Reiner W. Hartenstein
A decade of reconfigurable computing: a visionary retrospective. DATE (2001)
Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger
Synthesis and domain-specific optimization of KressArray-based reconfigurable computing engines (poster abstract). FPGA (2000)
Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger
Generation of Design Suggestions for Coarse-Grain Reconfigurable Architectures. FPL (2000)
Reiner W. Hartenstein, Thomas Hoffmann, Ulrich Nageldinger
Design-Space Exploration of Low Power Coarse Grained Reconfigurable Datapath Array Architectures. PATMOS (2000)
Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger
KressArray Xplorer: a new CAD environment to optimize reconfigurable datapath array. ASP-DAC (2000)
Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger
Mapping Applications onto Reconfigurable Kress Arrays. FPL (1999)
Reiner W. Hartenstein, Michael Herz, Ulrich Nageldinger, Thomas Hoffmann
An Internet Based Development Framework for Reconfigurable Computing. FPL (1999)
Reiner W. Hartenstein, Veljko M. Milutinovic
Configware: From Glue Logic Synthesis to Reconfigurable Computing Systems- Introduction. HICSS (1999)
Jürgen Becker, Reiner W. Hartenstein
Real-Time Prototyping in Microprocessor/Accelerator Symbiosis. International Workshop on Rapid System Prototyping (1998)
Reiner W. Hartenstein
Introduction to the Configware Minitrack: Hardware and Software Come Closer. HICSS (7) (1998)
Jürgen Becker, Reiner W. Hartenstein, Michael Herz, Ulrich Nageldinger
Parallelization in Co-Compilation for Configurable Accelerators. ASP-DAC (1998)
Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger
On Reconfigurable Co-processing Units. IPPS/SPDP Workshops (1998)
Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger
Exploiting Contemporary Memory Techniques in Reconfigurable Accelerators. FPL (1998)
Reiner W. Hartenstein, Michael Herz, Frank Gilbert
Designing for Xilinx XC6200 FPGAs. FPL (1998)
Reiner W. Hartenstein, Jürgen Becker
A Two-level Co-Design Framework for Xputer-based data-driven reconfigurable Accelerators. HICSS (5) (1997)
Reiner W. Hartenstein, Jürgen Becker
Performance Analysis in CoDe-X Partitioning for Structural Programmable Accelerators. CODES (1997)
Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Ulrich Nageldinger
Data scheduling to increase performance of parallel accelerators. FPL (1997)
Reiner W. Hartenstein, Jürgen Becker
Hardware/Software Co-Design for Data-Driven Xputer-based Accelerators. VLSI Design (1997)
William H. Mangione-Smith, Brad Hutchins, David L. Andrews, André DeHon, Carl Ebeling, Reiner W. Hartenstein, Oskar Mencer, John Morris, Krishna V. Palem, Viktor K. Prasanna, Henk A. E. Spaanenburg
Seeking Solutions in Configurable Computing. Computer 30 (12) (1997)
Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Ulrich Nageldinger
A Novel Sequencer Hardware for Application Specific Computing. ASAP (1997)
Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Ulrich Nageldinger
A Novel Universal Sequencer Hardware. ARCS (1997)
Rainer Kress, Reiner W. Hartenstein, Ulrich Nageldinger
An operating system for custom computing machines based on the Xputer paradigm. FPL (1997)
Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Rainer Kress, Ulrich Nageldinger
A Partitioning Programming Environment for a Novel Parallel Architecture. IPPS (1996)
Reiner W. Hartenstein, Jürgen Becker, Rainer Kress
Two-level Partitioning of Image Processing Algorithms for the Parallel Map-oriented Machine. CODES (1996)
Reiner W. Hartenstein, Jürgen Becker, Rainer Kress
Two-Level Hardware/Software Partitioning Using CoDe-X. ECBS (1996)
Reiner W. Hartenstein, Jürgen Becker, Rainer Kress, Helmut Reinig
High-performance computing using a reconfigurable accelerator. Concurr. Pract. Exp. 8 (6) (1996)
Reiner W. Hartenstein, Jürgen Becker, Rainer Kress, Helmut Reinig
CoDe-C: A Novel Two-Level Hardware/Software Co-Design Framework. VLSI Design (1996)
Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Rainer Kress, Ulrich Nageldinger
A Synthesis System For Bus-Based Wavefront Array Architectures. ASAP (1996)
Reiner W. Hartenstein, Jürgen Becker, Rainer Kress
An Embedded Accelerator for Real-Time Image Processing. RTS (1996)
Reiner W. Hartenstein, Jürgen Becker, Rainer Kress
Custom Computing Machines vs. Hardware/Software Codesign: From a globalized point of view. FPL (1996)
Reiner W. Hartenstein, Jürgen Becker, Rainer Kress, Helmut Reinig, Karin Schmidt
A Parallelizing Compilation Method for the Map-oriented Machine. ASAP (1995)
Reiner W. Hartenstein, Rainer Kress
A datapath synthesis system for the reconfigurable datapath architecture. ASP-DAC (1995)
Reiner W. Hartenstein
Hardware/Software Co-Design - Das aktuelle Schlagwort Inform. Spektrum 18 (5) (1995)
Reiner W. Hartenstein
Custom Computing Machines - Das aktuelle Schlagwort Inform. Spektrum 18 (4) (1995)
Reiner W. Hartenstein, Karin Schmidt
Combining structural and procedural programming by parallelizing compilation. SAC (1995)
Reiner W. Hartenstein, Rainer Kress, Helmut Reinig
A New FPGA Architecture for Word-Oriented Datapaths. FPL (1994)
Reiner W. Hartenstein, Rainer Kress, Helmut Reinig
A dynamically reconfigurable wavefront array architecture for evaluation of expressions. ASAP (1994)
Andreas Ast, Jürgen Becker, Reiner W. Hartenstein, Rainer Kress, Helmut Reinig, Karin Schmidt
Data-Procedural Languages for FPL-based Machines. FPL (1994)
Rainer Kress, Elmar U. K. Melcher, Reiner W. Hartenstein, Michel Dana
CMOS interconnect modelling for timing analysis. Microprocess. Microprogramming 37 (1-5) (1993)
Andreas Ast, Reiner W. Hartenstein, Rainer Kress, Helmut Reinig, Karin Schmidt
Novel High Performance Machine Paradigms and Fast- Turnaround ASIC Design Methods. FPL (1992)
Reiner W. Hartenstein, Alexander G. Hirschbiel, Karin Schmidt, M. Weber
A novel paradigm of parallel computation and its use to implement simple high-performance hardware. Future Gener. Comput. Syst. 7 (2-3) (1992)
Joachim Blödel, Markus Brandstetter, Peter Conradi, Walter Drangmeister, Reiner W. Hartenstein, Dietmar Schroeder
An Information Model Describing the Exchange of IC Technology Data. Electronic Design Automation Frameworks (1992)
Franz-Josef Brandenburg, Werner Freise, Winfried Görke, Reiner W. Hartenstein, P. Kühn, H. J. Schmitt
Gemeinsame Stellungnahme der Fakultätentage Elektrotechnik und Informatik zur Abstimmung ihrer Fachgebierte im Bereich Informationstechnik. Inform. Spektrum 14 (3) (1991)
Reiner W. Hartenstein, Alexander G. Hirschbiel, Karin Lemmert, Michael Riedmüller, Karin Schmidt, M. Weber
Xputer use in image processing and digital signal processing. VCIP (1990)
Reiner W. Hartenstein, Alexander G. Hirschbiel, M. Weber
Xputers: An Open Family of Non-Von Neumann Architectures. ARCS (1990)
Reiner W. Hartenstein, Alexander G. Hirschbiel, M. Weber
The Machine Paradigm of Xputers and its Application to Digital Signal Processing Acceleration. ICPP (1) (1990)
Reiner W. Hartenstein, Alexander G. Hirschbiel, M. Weber
Xputers: very high throughput by innovative computing principles. Jerusalem Conference on Information Technology (1990)
Reiner W. Hartenstein, Alexander G. Hirschbiel, M. Riedmüller, Karin Schmidt, M. Weber
Automatic Synthesis of Cheap Hardware Accelerators for Signal Processing and Image Processing. DAGM-Symposium (1990)
Reiner W. Hartenstein, Alexander G. Hirschbiel, M. Weber
A Novel Paradigm of Parallel Computation and its Use to Implement Simple High Performance Hardware. CONPAR (1990)
Gerold Alfs, Reiner W. Hartenstein, Andrea Wodtko
Explicit fault modeling and hierarchical test pattern generation in the KARATE system. Microprocessing and Microprogramming 27 (1-5) (1989)
Reiner W. Hartenstein, Karin Lemmert, Michael Riedmüller
system. Microprocessing and Microprogramming 27 (1-5) (1989)
Reiner W. Hartenstein
Microelectronics: VLSI design tools I. Microprocess. Microprogramming 24 (1-5) (1988)
Gerold Affs, Reiner W. Hartenstein, Andrea Wodtko
The KARL/KARATE System: Automatic Test Pattern Generation Based on RT Level Descriptions. ITC (1988)
Reiner W. Hartenstein, K. W. Jörg, U. Welters
MLED - Ein Mehrebenen Graphik Editor für den VLSI-Entwurf. GI Jahrestagung (2) (1988)
Reiner W. Hartenstein, Michael Ryba
Partitionierungsschemata für Rechnerstrukturen. GI Jahrestagung (2) (1988)
Joachim Blödel, Reiner W. Hartenstein, Wolfgang Nebel, Michael Ryba
A technology description method for generalized layout / circuit relations. Microprocess. Microprogramming 23 (1-5) (1988)
Gerold Alfs, Reiner W. Hartenstein, Andrea Wodtko
The KARL/KARATE system - integrating functional test development into a CAD environment for VLSI. ICCD (1988)
Reiner W. Hartenstein, Udo Welters
MLED: A multiple abstraction level graphical editor. Microprocess. Microprogramming 21 (1-5) (1987)
Reiner W. Hartenstein, Alexander Hirschbiel, M. Weber
A flexible architecture for image processing. Microprocess. Microprogramming 21 (1-5) (1987)
Reiner W. Hartenstein, U. Welters
Mehrebenenen-Graphik-Editor MLED als DBMS für VLSI-Simulation. Simulationstechnik (1987)
Reiner W. Hartenstein
Silicon Compiler - Das aktuelle Schlagwort. Inform. Spektrum 6 (4) (1983)
Reiner W. Hartenstein
Die "Neue Mikroelektronik" in der Informatik: Voraussetzungen und Auswirkungen. GI Jahrestagung (1982)
Reiner W. Hartenstein
KARL-II - eine Sprache zur Spezifikation beim Entwurf Kundenspezifischer Digitalbausteine. Angew. Inform. 24 (12) (1982)
Reiner W. Hartenstein
VLSI-Algorithmen - Das aktuelle Schlagwort. Inform. Spektrum 4 (2) (1981)
Reiner W. Hartenstein, Peter Liell
Ein Compiler für die Register Transfer-Sprache KARL-2. GI Jahrestagung (1980)
J. Dieckmann, Reiner W. Hartenstein, Werner Konrad
Software-Zuverlässigkeit mit Rechnernetz-Baukästen verteilter Programmierung. Hardware für Software (1980)
Reiner W. Hartenstein
VLSI-Bausteine in geringen Stückzahlen für Spezial-Anwendungen. Elektron. Rechenanlagen 22 (4) (1980)
Reiner W. Hartenstein
Microprogramming concepts - a step towards structured hardware design. MICRO (1974)
Reiner W. Hartenstein
Konzepte der Mikroprogrammierung. ARCS (1974)
Reiner W. Hartenstein
Letter to membership from incoming chairman (CAN, Oct. 73). SIGARCH Comput. Archit. News 3 (1) (1974)
Reiner W. Hartenstein, Klaus D. Mueller
A microprogrammable display processor concept. MICRO (1973)
Reiner W. Hartenstein
Increasing Hardware Complexity - A Challenge to Computer Architecture Education. ISCA (1973)

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Publication Activity (10 Years)

Top Topics

Top Venues

Reiner W. Hartenstein