Michael Herz

Publication Activity (10 Years)

Years Active: 1996-2002
Publications (10 Years): 0

Kaiserslautern University of Technology, Germany (PHD)

Education History

Kaiserslautern University of Technology, Germany

PHD

Publications

Michael Herz, Reiner W. Hartenstein, Miguel Miranda, Erik Brockmeyer, Francky Catthoor
Memory addressing organization for stream-based reconfigurable computing. ICECS (2002)
Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger
Synthesis and domain-specific optimization of KressArray-based reconfigurable computing engines (poster abstract). FPGA (2000)
Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger
Generation of Design Suggestions for Coarse-Grain Reconfigurable Architectures. FPL (2000)
Michael Herz
Agilent's Key Technologies in Remote System Management. CLUSTER (2000)
Michael Herz
Remote System Management Principles. CLUSTER (2000)
Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger
KressArray Xplorer: a new CAD environment to optimize reconfigurable datapath array. ASP-DAC (2000)
Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger
Mapping Applications onto Reconfigurable Kress Arrays. FPL (1999)
Reiner W. Hartenstein, Michael Herz, Ulrich Nageldinger, Thomas Hoffmann
An Internet Based Development Framework for Reconfigurable Computing. FPL (1999)
Michael Herz, Thomas Hoffmann, Ulrich Nageldinger, Christian Schreiber
Interfacing the MoM-PDA to an Internet-based Development System. HICSS (1999)
Michael Herz, Thomas Hoffmann, Ulrich Nageldinger, Christian Schreiber
XMDS: The Xputer Multimedia Development System. HICSS (1999)
Jürgen Becker, Reiner W. Hartenstein, Michael Herz, Ulrich Nageldinger
Parallelization in Co-Compilation for Configurable Accelerators. ASP-DAC (1998)
Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger
On Reconfigurable Co-processing Units. IPPS/SPDP Workshops (1998)
Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger
Exploiting Contemporary Memory Techniques in Reconfigurable Accelerators. FPL (1998)
Reiner W. Hartenstein, Michael Herz, Frank Gilbert
Designing for Xilinx XC6200 FPGAs. FPL (1998)
Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Ulrich Nageldinger
Data scheduling to increase performance of parallel accelerators. FPL (1997)
Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Ulrich Nageldinger
A Novel Sequencer Hardware for Application Specific Computing. ASAP (1997)
Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Ulrich Nageldinger
A Novel Universal Sequencer Hardware. ARCS (1997)
Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Rainer Kress, Ulrich Nageldinger
A Partitioning Programming Environment for a Novel Parallel Architecture. IPPS (1996)
Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Rainer Kress, Ulrich Nageldinger
A Synthesis System For Bus-Based Wavefront Array Architectures. ASAP (1996)

Michael Herz.css-eqlu8i{font-size:small;padding-left:4px;}

Publication Activity (10 Years)

Michael Herz